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How active RGPIO bus

Started by xanyanou, April 19, 2017, 05:28:43 PM

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xanyanou

Hello,

I recently buy a carrier board te0701 with a te0710 module.
In a first time, I am trying to use leds to be sure that my fpga is working fine.
After consulting these pages https://wiki.trenz-electronic.de/display/PD/TE0701+CPLD and https://wiki.trenz-electronic.de/display/PD/TE0701+TRM,
I don't understand how RGPIO bus is working.
How I can active it and wich pins from the FPGA to the CPLD refers to this bus ?

Thank you

JH

Hello,

you need a special IP from us. We have no example design for 7 series online with this IP.
I will prepare this IP with some documentation in the next two weeks. I'll inform you, when it will be available.

br
John

eroxyde

Hi!
I would be interested in thids IP as well.

Thanks !

JH

Hi,
i've upload a IP to get access:
Short description:
Download:Use Master Interface only on IP. In case of TE0720 and TE0701 and connect the 3 external IOs to:set_property PACKAGE_PIN U7 [get_ports RGPIO_M_EXT_0_clk]
set_property PACKAGE_PIN R6 [get_ports RGPIO_M_EXT_0_rx]
set_property PACKAGE_PIN R7 [get_ports RGPIO_M_EXT_0_tx]
set_property IOSTANDARD LVCMOS33 [get_ports RGPIO_M_EXT_0_clk]
set_property IOSTANDARD LVCMOS33 [get_ports RGPIO_M_EXT_0_rx]
set_property IOSTANDARD LVCMOS33 [get_ports RGPIO_M_EXT_0_tx]

IO Standard depends on VADJ. You use other voltage than 3.3V change LVCMOS...
TE0701 RGPIO Pins:
I've currently no TE0701 on place, if something is not clear, let me know.
@Xanyanou: Sorry for the late response. I completely forgot to do this.
brJohn