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TE0300 USB communication

Started by mfa, October 07, 2010, 04:24:55 PM

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mfa

Hello Forum!

I am using a TE0300-01BM micromodule for a signal processing application. The fact that the Xilinx EDK Suite is kind of expensive and the nature of our project lead us to the decision to use the ISE WebPack Software for development in verilog. This means that I cannot use the microblaze reference design...

My question is now how to get a simple USB communication up and running that is able to stream data to a PC for offline processing. The first idea I had was to develop a customized version of the XPS_FX2 module that streams data to the FX2 uC and using the TE0300 API on the PC side to save the received data to a file. However, I am unsure if there maybe is an easier solution. Furthermore I am unsure how to start developing the module because I don't really know what the firmware is doing on the FX2 uC.

Maybe you can suggest some starting point or a better solution?

Kind regards,
Martijn Arts

Ales Gorkic

Dear Martin,

The best option to my opinion is to take the FX2 communication core:
TE03xx-development-suite\MyProcessorIPLib\pcores\xps_fx2_v1_10_a\hdl\vhdl\fx2_core.vhd
You you have all the functionality there.
Read the :
TE03xx-development-suite\MyProcessorIPLib\pcores\xps_fx2_v1_10_a\doc\xps_fx2_v1_10_a.pdf
for a reference on register interface.

The only thing which is missing is a TX_FIFO which has 32Bit output and is FWFT (first word fall through) type.
Unfortunatelly it is generated on the fly with xps_fx2_v2_1_0.tcl script to enable user to select different sizes. You can take this script as a reference.

You can also use the I2C register interface (12bytes) for sending commands:
i2c_slave_core.vhd (an all the submodules)

The pinout of both interfaces is in the
TE03xx-development-suite\reference-TE0300-01-EDK-12-2\data\system.ucf

I hope you will manage to assemble ISE design with this instructions.

Best regards,

Ales

mfa

Hi Ales!

Thanks for your quick reply! I had a look at the files you mentioned and put together a little test design. Now, I am able to stream data via USB (at high speed ~ 34MB/s) and I can read it out with the TE0300 API.

However, I am having problems with data integrity. More specifically, I am getting shifts of 8 - 24 bits. This happens the first time after 1024 words and then everytime after another 512 words that are being sent. I tried setting the C_TX_FIFO_CLK_180 to 1 in the FX2 core, but this did not help.

Secondly I am expieriencing a weird place & route error:

QuotePlace:619 - This design is using a Side-BUFG site due to placement constraints on a BUFG, DCM, clock IOB or the loads of these components. It is recommended that Top and Bottom BUFG sites be used instead of Side-BUFG sites whenever possible because they can reach every clock region on the device. Side-BUFG sites can reach only clock regions on the same side of the device and also preclude the use of certain Top and Bottom BUFGs in the same clock region.

From your .ucf file I can see, that you did not have to override this error with a
NET "USB_IFCLK" CLOCK_DEDICATED_ROUTE = FALSE; statement. Frankly, I cannot figure out, why this error is happening at all, since I did not put any other constrains to the USB_IFCLK than the ones in your design.

I have uploaded my design and some individual files, so you can have a quick look, if you can spare the time:

* the .ucf file: http://mfa.devtty0.de/misc/usb_test/USB_test.ucf
* the verilog code: http://mfa.devtty0.de/misc/usb_test/usb_send_test.v
* a binary dump of the USB data: http://mfa.devtty0.de/misc/usb_test/USBdump.bin
* the complete zipped design:  http://mfa.devtty0.de/misc/usb_test/usb_test.zip

Kind regards,
Martijn

Ales Gorkic

Dear Martijn,

First of all I would check if the API returns any timeouts in TE300_GetData.
The second thing to check is the Packet End assertion.


I hope it helps.

Ales

Hengist

The release of the third generation Trenz Electronic USB FX2 Suite made this post obsolete. Please access current documentation and resources here: TE USB FX2 Suite.