Trenz Electronic Products > Trenz Electronic FPGA Modules

Beginner using FPGA

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Thorsten Trenz:

--- Quote from: thef on October 08, 2010, 04:46:45 AM ---Are there any switch setting on the TE board that I need to set ? or any configuration in the xilinx that need to be configure ?

--- End quote ---

That depends on the problem. Does the DONE LED lit up? If not, then most probably you have to set the startup constraints in ISE to CCLK.
If this setting is correct, then you may have a problem in generating the FWU file.
But without more information, we can only guess.

I strongly recommend to use a JTAG adapter for development. This way you can be sure your bitfile works before building a FWU file.

best regards
Thorsten Trenz

I have a parallel port JTAG, will it work with TE0320 board ? By the way do you have a simple example project that make use of the two switches which you could provide to help me kick start this development.

Danke  :)

Thorsten Trenz:
JTAG IO's are powered from VCCAUX, which is 2.5V on your module variant. So if your JTAG cable is capable of 2.5V JTAG chain it will work. In any case, use the Vref on the JTAG connector to power the output drivers of your JTAG cable.

If your JTAG cable is capable of 3.3V JTAG chain only, you can put 220 OHM series resistors between the module and your cable, but this is on your own risk.

Please note, that it is recommended to set the boot mode to JTAG only when using the JTAG cable. See the TE0320 manual for the proper switch positions.

best regards
Thorsten Trenz


--- Quote from: Horsa on October 07, 2010, 10:16:06 AM ---
--- Quote from: thef on October 07, 2010, 09:49:10 AM ---Do you have a simple example that I can try and download and try ?

--- End quote ---
Yes, we have.

--- End quote ---


--- Code: ----- Trenz Electronic GmbH
-- sample project: tests push buttons and user LEDs
-- version 1.00 (2010-10-09)
-- verified hardware: TE0320-00-EV01

library ieee;
use ieee.std_logic_1164.all;
-- use ieee.numeric_std.all;  -- recommended library for synthesizable arithmetics

entity top is port (
  push_button_1, push_button_2                   : in  std_logic;
  user_led_1, user_led_2, user_led_3, user_led_4 : out std_logic
end entity top;

architecture top_architecture of top is

  user_led_1 <= not(push_button_2);  -- push-buttons_1 is farhter from user_led_1
  user_led_2 <= not(push_button_1);  -- push-buttons_2 is nearer  to   user_led_2
  user_led_3 <= not(push_button_1) or not(push_button_2);  -- logical or -- negative logic
  -- user_led_3 <= (push_button_1) nand (push_button_2);   -- equivalent logic function
  user_led_4 <=
    '0'  -- turn off test signal when both push buttons are pressed
    when (push_button_1 = '0') and (push_button_2 = '0')
    '1' -- test signal = always on
end architecture top_architecture;

--- End code ---


--- Code: ---# switch S3 = signal PB1 (push button 1)
NET "push_button_1" LOC = "U23" | PULLUP;
# switch S4 = signal PB2 (push button 2)
NET "push_button_2" LOC = "R22" | PULLUP;

# LED D5 = signal UL1 (user led 1)
NET "user_led_1" LOC = "R20";
# LED D6 = signal UL2 (user led 2)
NET "user_led_2" LOC = "V23";
# LED D7 = signal UL3 (user led 3)
NET "user_led_3" LOC = "R19";
# LED D8 = signal UL4 (user led 4)
NET "user_led_4" LOC = "U24";

--- End code ---

Xilinx ISE 12.2 project package available upon request. It will be released in the next TE03xx software pack revision.

How do I request for the 12.2 ISE support package ? :)


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