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ZynqBerry SPI

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JH:
Hi,
check these pages:
https://www.hackster.io/news/microzed-chronicles-using-spidev-in-petalinux-18ff937807c5
https://www.beyond-circuits.com/wordpress/tutorial/tutorial26/


br
John

ChanceTran:
Hi....Comprehend the contrast between the MIO and EMIO choices found in the IO section. The MIO (Multiplexed IO) pins are a proper arrangement of devoted pins that specific fringe capacities can be appointed to. These are traded as a feature of the FIXED_IO port that Vivado made during the Block Automation prior. MIO's are simply associated with the PS and not to the PL.

In the event that a fringe is directed through EMIO (Extended Multiplexed IO), Vivado will make an extraordinary port for that fringe on the Zynq PS block that can be relegated like some other sign in the PL. EMIOs are basically wires from the PS to the PL.

JH:
Hi, sorry, maybe I misunderstood something but that was just a statement and not a question, right?

br
John

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