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Custom Carrier Module : Recommendations for power distribution system for TE0712

Started by spr, January 10, 2017, 06:33:19 PM

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spr

Hello,

We are designing a custom carrier board for the TE0712 -200 module.  I have the following questions regarding the power distribution system :

1) Since, all our I/O lines are 3.3 V rails, I am planning to connect all the power pins of the module (PWR_1, PWR_2, VCCIOA, VCCIOB, VCCIOC and VCCIOD) to 3.3 V. Is this fine ?

2) All the above 3.3 V connections will be sourced from a single 3.3 V power chip. Is this approach fine ?

3) What is the maximum current that my power chip should handle which will ensure the operation of the TE0712 module under all circumstances (with all 4 GTx lines (only Rx) being enabled and with Artix 7 200 FPGA resources more than 80% utilized)  ?

4) I guess the various other voltages required by the Artix 7 FPGA is generated by the TE0712 module itself (on-board) including the GTx reference voltages (1.8/1.0/1.2 V). Is this correct ?

5) Would it be a good approach to use 0.1 uF decoupling capacitor for each Vcc input pin (including the I/O bank Vcc pins - VCCIOA/B/C/D) ? In the schematic of TE0703 I see that a single 10 uF capacitor has been used for a set of Vcc connections (PWR_1 and PWR_2) and no decoupling capacitor for I/O bank Vcc pins..

6) How should the JTAGVref output pin on the JB2 connector be handled ? Should this pin be connected to the actual JTAG connector or can I leave this pin open and directly connect the 3.3 V from the my carrier board's power chip to the JTAG connector ?

Any help would be greatly appreciated !!

PS : Some questions might be a bit trivial as I am new to board design. Thanks in advance for your patience !

Regards,
SPR

Thorsten Trenz

Hello,
1, 2) Take care to power the VCCIO only when the module is powered up correctly. We recommend to use the 3.3V output (e.g. JM2 Pin10,12) for powering the VCCIO. If you need more then 100mA on this line, use it to enable the VCCIO supply. Do not connect 3.3Vin with the 3.3V output and VCCIO directly.
Powering Vin and 3.3Vin from the same 3.3V supply is fine.

3) That is dependent on your design. 4-6 A should be sufficient.

4) Yes

5) All needed capacitors are already on the module. 100nF is fine to add.

6) JTAGVREF is an output and should be used to power the IO Buffer of the JTAG circuit. Even the module JTAG is 3.3V, we recommend to use this line for compatibility reasons. If you use other 3.3V, the same as in 1) applies. Do not feed any voltage to any pin, when the module is not powered up, use the 3.3V output to verify this.

Additional hint: Read the module integration guide and the connector description before starting your baseboard:

https://wiki.trenz-electronic.de/display/PD/General+4x5+cm+Modules+Documentation

Best Regards,
Thorsten Trenz