Author Topic: A FPGA LED Control Project  (Read 3021 times)


  • Active Member
  • *
  • Posts: 5
A FPGA LED Control Project
« on: December 13, 2016, 08:56:36 AM »

This  project is a simulation of a room in which lights are switched on/off based on the amount of people in the room. The switches of the FPGA board correspond to how many people are in the room (3 bits, or up to 7 people). The seven segment display of the board is used as a countdown timer in which the final light shut off after one minute when the room in vacated. The number of lights on will correlate to the amount of perceived people in the room (1 LED for 1 person, 2 LEDs for 2 people, 3 LEDs for 3 people, etc). The timer will reset to 60 seconds once the room is occupied again.
Step 1: Materials

▲8 Wires
▲7 LEDS (TLHB4201 datasheet)
▲7 resistors (330 Ω)
▲1 MicroUSB cable
▲1 FPGA Basys 3 board
▲1 Breadboard
▲1 Computer with VHDL (not pictured)
Step 2: Setup
The hardware output of the project is the breadboard with the connected LEDs. The output on the LEDs are the result of the inputs on the FPGA Basys 3 board. Construct a simple LED resistor circuit on the breadboard as pictured above. The grounding of the circuit goes to GND of the PMOD port on the Basys 3. Repeat the process six more times in order to have seven separate LED resistor circuits. If there is any confusion as to how to make an LED resistor circuit, here is a great instructable by wrcoakle for reference:

It is very important to have a resistor of an appropriate value in each circuit as it will prevent the LEDs from being short-circuited and burnt out. The resistance of the LED alone is not enough to impede the voltage from the source. We used 330 Ωresistors.
Step 3: Clock Divider Module

Our clock module is nearly the same as the one provided to us in lab, with the exception of a different frequency. The purpose of the clock is to provide an oscillating signal which a circuit can utilize. Our intention was to use the clock divider module as a clock which counted actual seconds. In order to slow down the oscillating signal that the clock outputted, we had to change the frequency of the clock in order to output a signal every second.

entity clk_div2 is<br>    Port (  clk : in std_logic;
           sclk : out std_logic);
end clk_div2;
architecture my_clk_div of clk_div2 is
   constant max_count : integer := (50000000); 
   signal tmp_clk : std_logic := '0';
   my_div: process (clk,tmp_clk)             
      variable div_cnt : integer := 0;   
      if (rising_edge(clk)) then   
         if (div_cnt = MAX_COUNT) then
            tmp_clk <= not tmp_clk;
            div_cnt := 0;
            div_cnt := div_cnt + 1;
         end if;
      end if;
      sclk <= tmp_clk;
   end process my_div;
end my_clk_div;
I just finished these three parts. I WILL update when i finished the next step.I WANT to write them down.Thanks !