DIPFORTy1 JTAG Programming

[andi8086]

Hi,

I am completely new to FPGA and JTAG programming. I have recently purchased a DIPFORTy1 board, which is really amazing! However, I have no idea, if I correctly interpret the documentation. I have found a picture of a pinout. I have the following questions:

a) Is the JTAG pinout independent of the programmed FPGA / SPI Flash?
b) I am using a Digilent JTAG HSx Adapter (USB to FT232H Serial Device), can I connect it according to the pinout given there?
https://wiki.trenz-electronic.de/pages/viewpage.action?pageId=20612010

c) Is the DIP40 pinout on that page specific to the Propeller-Image and is that Propeller pre-programmed to the FPGA?
d) How to I connect power to the DIPFORTy1? Is it enough to connect power to J1?

Any help is very much appreciated!

[Antti Lukats]

Hi,

I am completely new to FPGA and JTAG programming. I have recently purchased a DIPFORTy1 board, which is really amazing! However, I have no idea, if I correctly interpret the documentation. I have found a picture of a pinout. I have the following questions:

a) Is the JTAG pinout independent of the programmed FPGA / SPI Flash?
b) I am using a Digilent JTAG HSx Adapter (USB to FT232H Serial Device), can I connect it according to the pinout given there?
https://wiki.trenz-electronic.de/pages/viewpage.action?pageId=20612010

c) Is the DIP40 pinout on that page specific to the Propeller-Image and is that Propeller pre-programmed to the FPGA?
d) How to I connect power to the DIPFORTy1? Is it enough to connect power to J1?

Any help is very much appreciated!

1) yes
2) for HS you need "wire adapter", our own flexible JTAG adapter TE0790 can be inserted directly without special wiring (but adapter needs custom config to map the jtag pins for dipforty)
3) pinput is propeller DIP40 yes, no it is not preprogrammed as prop
4) you can power from any pinheader 3.3V pin. should you have long wires to 3.3V power supply it may cause problem, voltage drop then a large CAP at pins is needed, if you have low impedance power supply, then that cap is not needed

[andi8086]

Thank you very much

[andi8086]

Hi,

now I tried to program the FPGA, which seems to succeed, but I had no idea about the correct design to connect the PS to the GPIO pins correctly and how to make Serial and SPI Flash working. I have found an example project under support on trenz-electronic.de main site,
however, when I try to run the tcl script to generate the block design, it tells me:

# create_root_design ""
ERROR: [IP_Flow 19-3461] Value 'dip_32bit' is out of the range for parameter 'GPIO BOARD INTERFACE(GPIO_BOARD_INTERFACE)' for BD Cell 'axi_gpio_0' . Valid values are - Custom
INFO: [IP_Flow 19-3438] Customization errors found on 'axi_gpio_0'. Restoring to previous valid configuration.
INFO: [Common 17-17] undo 'set_property'
ERROR: [Common 17-39] 'set_property' failed due to earlier errors.

    while executing
"rdi::add_properties -dict {CONFIG.GPIO_BOARD_INTERFACE dip_32bit CONFIG.USE_BOARD_FLOW true} /axi_gpio_0"
    invoked from within
"set_property -dict [ list  CONFIG.GPIO_BOARD_INTERFACE {dip_32bit}  CONFIG.USE_BOARD_FLOW {true}  ] $axi_gpio_0"
    (procedure "create_root_design" line 39)
    invoked from within
"create_root_design """
    (file "/home/andreas/dipforty/examples/test_board/block_design/zsys_bd.tcl" line 1523)

It is from
http://www.trenz-electronic.de/fileadmin/docs/Trenz_Electronic/TE0722/Reference_Design/2016.2/test_board/te0722-test_board_noprebuilt-vivado_2016.2-build_04_20160714114808.zip

is there any working example project for Vivado that shows me the correct Block design and the Constraints fitting the DIPFORTy1 board?
If not, can you please provide one?

Kind regards
Andreas

[JH]

Hi,

to generate the vivado reference design on linux, follow Option 2 of this description (we will provide some start shell scripts for linux on vivado 2016.4 release): https://wiki.trenz-electronic.de/display/PD/Vivado+Projects
You can you this project as template. The Example used the XMOD-Adapater for UART.
Attention, this PCB has no PS-RAM. If you configure the Flash with wrong FSBL, it will freeze and is not longer accessible. See: https://wiki.trenz-electronic.de/display/PD/DDR+less+ZYNQ+Design
We include a FSBL Template for SDK, with this modifications.
Here are some links for TE0722:
 https://wiki.trenz-electronic.de/pages/viewpage.action?pageId=20612010
 https://shop.trenz-electronic.de/en/Download/?path=Trenz_Electronic/TE0722

Please read the xilinx basic documents to understand the design flow of Xilinx FPGAs:
 Here is a link from our wiki with the basic documents as reference:
   https://wiki.trenz-electronic.de/pages/viewpage.action?pageId=14746264
 Or use Xilinx Website
   https://www.xilinx.com/support.html

BR
John

[andi8086]

Hi John

Thank you very much!!

I just wrote a reply that it did not work... but then I saw, that I have to specify TE0722-02 and not TE0722 as PARTNUM, then it worked

Kind regards
Andi

[andi8086]

Hi,

so finally, the first "Hello-World" example worked out of the box. (The tip with XMOD Connector was good, it reminded me of connecting a ttyUSB adapter along with the JTAG adapter).

1.) So now I would like to create a boot.bin, but SDK only creates an ELF file from my FSBL. And I have no BIF file. How do I create a boot.bin which incorporates my FPGA bitstream?
Some people on the internet talk about a dialog that apears when clicking onto "Xilinx Tools / Create boot image". But there is no dialog... at least I see nothing.. it just compiles the ELF.

2.) Why am I not seeing the DEBUG messages of my FSBL on the tty terminal... I just see "Secondary FPGA Image loaded..." - however, the JTAG output confirms that PS7_Init... etc. functions ran successfully. (I disabled the DDR_Init check).

3.) After some seconds or minutes, the big LED on the board flashes up shortly and the red FPGA programming LED goes on and stays on. I have to turn off and back on the power supply. Also.. when I do that... some times it won't boot up, but the big LED starts blinking white with short pulses around 20 times and then the same with permanently enabled red FPGA LED. I have already added an electrolytic capacitor to stabilize the power supply (I use an ATX PC power supply).
JTAG: Vdd = 3.3V, GND = GND
ttyUSB: GND = GND, VCC not connected

Kind regards
Andi

[JH]

Hi,

1.) See https://wiki.trenz-electronic.de/display/PD/SDK+Projects
-Modify FSBL for DDR Less or include our FSBL template in the SDK repo and use this.
 
2.) Is Debug messages are enabled? Do you select the correct UART for FSBL --> BSB Settings in SDK
-See https://wiki.trenz-electronic.de/display/PD/Zynq+Troubleshooting+Guide

On our Wiki are some references to basic Xilinx documentation: It described how do use Xilinx Tools: https://wiki.trenz-electronic.de/pages/viewpage.action?pageId=14746264

3.) Which Red LED did you mean? Done LED(D6) pr D1/D3 (if assembled) or D5? See: https://wiki.trenz-electronic.de/pages/viewpage.action?pageId=20612010
Normally there is a initial Design on the PCB, maybe  that's the reason for blinking LED. Done-LED can be a problem, but this LED can also be USER-controlled after startup. I did not now the shipped design.

br
John
 

[andi8086]

Hi,

1.) I have read everything about the FSBL and DDR-less design and I think I implemented it correctly. But, I cannot open this "Create Boot Image" Dialog... Nothing appears. Maybe it is a bug in Eclipse running on my Arch Linux / Awesome Window Manager / GTK installed. I will try a VM with another Linux. Also sometimes, the tabs in the dialogs don't change when I click onto the labels. This Eclipse seems to be very unstable.
If I had a BIF file, I could use the shell tools manually to create a boot.bin.

2.) Yes, I did the following:
- I set the FSBL_DEBUG preprocessor definition in the include file, where it is checked - to force it.
- I started the FSBL Project via "Run on Hardware". Maybe that is not possible this way?
Maybe the board boots with its own FSBL and mine is not executed at all?

3.) I mean the DONE LED. If it were user controlled, I would not know from where and it should not change its behavior, if no SD card is inserted. This only happens sometimes after a few minutes and with the soft propeller design loaded it did not happen so far. Maybe the CPU cores do strange things if they are idle for a longer period of time?

KR
Andi

[Antti Lukats]

BIF file is simple text file, you can create in notpad or whatever editor you like. then use command line tools to create boot.bin

[JH]

1. You can download the larger Zipfile, there is a bif included in the prebuilt folder: https://shop.trenz-electronic.de/en/Download/?path=Trenz_Electronic/TE0722/Reference_Design/2016.2/test_board
 or write it by yourself.
2. How did you start your FSBL? With SDK Debugger, if yes than yours  should be used. If you did not create a boot.bin or with SDK-Debugger with your FSBL, the shipped version from Flash will be started. On TE0722 Boot Mode is set to Flash.
 Debugging see: https://wiki.trenz-electronic.de/display/PD/SDK+Projects#SDKProjects-DebugSoftwareApplication
3.If the shipped version is started, it can be, that the Done LED is used as normal LED after Booting. If not, there will be a problem with your PCB, maybe Power and the system restarts. Please try debugging your FSBL first. And tell me if it works.
br
John

[andi8086]

Hi,

@Antti: thank you. I got it, that I only have to specify the filenames within the BIF.

@John: So I abandoned the idea of writing a FSBL... I have no idea what is going on. However,... I cannot print anything via UART, since UART is connected by FPGA and FPGA is not programmed when FSBL is running, so I assume I will never see any output I know that FSBL should load bitstream in the end... but this is not happening and there is no point in debugging and I will just use the factory boot loader... >.< for now.

So at the moment I try to stick to something simpler.... I just wanted to switch a GPIO Pin... and drive an LED with it. I loaded a GPIO example and am able to start the App via JTAG.

FPGA is programmed with the Reference design. The pins of the DIP40 package are connected to the AXI_GPIO Channel 1, if I am not mistaken. 32 bits means 32 I/O ports.

So next problems of course arose:

In my app, I call
Status = XGpio_Initialize(&Gpio, GPIO_EXAMPLE_DEVICE_ID); which returns XT_SUCCESS (checked via print).

GPIO_EXAMPLE_DEVICE_ID... is XPAR_GPIO_0_DEVICE_ID, which is  XPAR_AXI_GPIO_0_DEVICE_ID, which is 0... wonderful.
But correct? I have no idea...

From the IP Block design I read (maybe I am wrong, maybe some of the designers knowing that board and the ref implementation can have a look?) that pin 1 of the DIP40 (P0) is connected to gpio_dip_32bit[0] ? Which would mean that axi_gpio[0] is also this pin?

Then I call
XGpio_SetDataDirection(&Gpio, LED_CHANNEL, ~LED);

with LED_CHANNEL = 1, and LED = 0x01 (bit zero set).

which freezes everything and the chip is not responding to anything till I reset it. How the hell (excuse me) can I tell how I can drive one of the gpio pins....

How can I control the I/O Pins from within a simple app?

[Update: I just had the idea to set the i/o pin to PULLUP in the constraints and with this trick I saw my LED lightening... so I know now, that the pin is P0 and that it is gpio_dip32[0] but still no idea how to manage it in app software]

Kind regards

[JH]

Hi,

the XMOD UART goes through the PL part (see BlockDesign), so UART is only available, if PL is configured. Try the following:
1. Open SDK with HDF from Reference Design and generate modified FSBL.
2. Modify FSBL BSP settings (system.mss): Click Modify this BSP's Settings--> Click on standfalone -> set stdin and stdout to axi_uartli_1
3. Click Xilinx Tools --> Program FPGA : Program FPGA with Reference Design Bitstream.
4. Open Uart Console with correct port (see Win device manager) and Baudrate 9600 (siehe UART Lite IP in BlockDesing)
5. Right Click on fsbl project -->Debug As-->Launch on HW (System Debugger)
SDK Debugging View will be open. You can step throw the code with F5 or F6 or GUI Buttons.

If you will check the loc constrains, you can run Vivado Synthesis (or Implement), after that open Synthesized Design and set View to I/O Planning All Used IOs are displayed in the I/O Ports Table.

Did you use the AXI GPIOs or the Zynq GPIOs which are mapped to MIOs? TE0722 Pin header are connected to AXI GPIO core. If your system freeze, the system get no response from the interface.

Please try FSBL Debugging at first, after that we check the second problem.

BR
John

[JH]

I forgot, you use linux.
Check COM Ports: dmesg |grep tty
Minicom UART Console: sudo minicom -8 -b 9600 -D /dev/ttyUSB1

br
John

[angeloa13]

Hello, I am a student from Mexico and I would like to ask you a favor, if you could teach me how to program a "hello world" in Dipforty, I can program the hardware and then program the software but manually, but by turning off the Dipforty and turning it on again only the hardware is programmed and it does not load the software application, I need that when I turn on the dipforty hardware and software are running. I don't know what I'm doing wrong or what configuration I'm not doing, do you think you can help me?

"Do not add "hello.elf" as application to the BOOT.BIN, it would yield in non bootable boot image
Loading application to be run after bitstream loading is also possible, more FSBL changes are needed then."

what changes need to be made in the FSBL?

[JH]

Hi,

Dipforty is without DDR, so you has default only OCM available for application (OCM is very small and normally for fsbl). Default setups from Xilinx tools will not check this.

We have a 19.2 reference design online:

    https://wiki.trenz-electronic.de/display/PD/TE0722+Test+Board

Downloads includes also prebuilt binaries to test.

The easiest way is to add your application (hello world printout) into the FSBL source code, as long as the FSBL with your code is small enough it will fit into the OCM.

Alternatives(we haven't examples for this alternatives):

    Add PL Block ram as memory to the the zynq PS system
    use Flash as RO Memory:
    http://www.wiki.xilinx.com/Zynq-7000+AP+SoC+Boot+-+Booting+and+Running+Without+External+Memory+Tech+Tip
    https://www.xilinx.com/support/answers/54760.html


Note: Pay attention with Dipforty, you can brick the SoC, see: https://wiki.trenz-electronic.de/display/PD/DDR+less+ZYNQ+Design

br
John

[angeloa13]

my application is very small
"The easiest way is to add your application (hello world printout) into the FSBL source code, as long as the FSBL with your code is small enough it will fit into the OCM."
in which part of the FSBL do you have to put the code?

[JH]

Hi, see our FSBL app source code:
https://wiki.trenz-electronic.de/display/PD/TE0722+Test+Board#TE0722TestBoard-zynq_fsbl_app
--> Source location: \sw_lib\sw_apps

br
John