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TE0726-ZynqBerry / CPLD-Functionality

Started by wige, June 23, 2016, 04:28:06 PM

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wige

I have managed to get the ZynqBerry up and running including camera support relatively fast. Good job, Trenz-Team!

When trying to understand the schematic I recognized the Lattice CPLD which is connected to the LEDs, UART1, 2 PS7-GPIOs, 2 Camera-GPIOs and the DSI port...

Is there any description on what functionality is "hidden" inside the CPLD?

Or more specifically:
1. What can controlled by the two PS7-GPIOs?
2. What is the reason for connecting the DSI-Port to the CPLD as well as the Zynq?
3. Are the two ZynqBerry-LEDs user controllable or are just directly connected to the UART via the CPLD?
4. How to control the CSI-GPIOs? (and: does anybody have further infos on the RPI camera GPIOs? I have found some info in the web, guessing that one controls the CAM-LED and the other one controls the CAM power. Is this correct?)

Many thanks in advance
Winfried


Antti Lukats

hi

we are shipping the TE0726 with very basic functionality in the CPLD. As the CPLD can be updated by the user, and we plan to make an update also, we have not fully documented the initial release version. It basically loops through JTAG and UART and GPIO's to camera.

CAM GPIO:

correct one is backlighht, one is power on control

DSI port is connected to CPLD as we did run out PL IO pins, and we did not know if lows speed signaling is needed on D0 only, or also on other DSI lines, so the CPLD works as backup option to enable low speed signalling on all DSI lines.