TE0712 - How to use the clock input

[bjoernr.]

Hey,
in my project im stuck on getting the clock into the FPGA. I use the TE0712 with the TE0703 carrier board.
As referred to the wiki the clock output from the clock generator goes to pin F7/E6 from the FPGA.

If i try to do the implementation in Vivado i get the following error:

Code Select Expand

[Place 30-574] Poor placement for routing between an IO pin and BUFG. If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING. However, the use of this override is highly discouraged. These examples can be used directly in the .xdc file to override this clock rule.
< set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets MGT_CLK0_P_IBUF] >

MGT_CLK0_P_IBUF_inst (IBUF.O) is locked to IPAD_X1Y44
and MGT_CLK0_P_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y31

my constraint file:

Code Select Expand

set_property PACKAGE_PIN J16 [get_ports LED1]
set_property PACKAGE_PIN M17 [get_ports LED2]
set_property IOSTANDARD LVCMOS33 [get_ports LED2]
set_property IOSTANDARD LVCMOS33 [get_ports LED1]

create_clock -period 10.000 -name MGT_CLK0_P -waveform {0.000 5.000} [get_ports MGT_CLK0_P]

set_property PACKAGE_PIN F6 [get_ports MGT_CLK0_P]

and my vhdl file:

Code Select Expand

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity blinki is
    Port ( LED1       : out STD_LOGIC := '1';
           LED2       : out STD_LOGIC := '1';
           MGT_CLK0_P : in  STD_LOGIC);
end blinki;

architecture Behavioral of blinki is

signal counter : Integer;
begin
blink : process(MGT_CLK0_P,counter)
    begin 
    If rising_edge(MGT_CLK0_P) then
        counter <= counter + 1;
    end If;
    If counter = 12500000 then
        LED1 <= '1';
        LED2 <= '1';
    end If;
    If counter = 25000000 then
        LED1 <= '0';
        LED2 <= '0';
        counter <= 0;
    end If;   
end process blink;
end Behavioral;


could someone please explain my i get the error and how i could fix that ?

Thanks, Björn

[Oleksandr Kiyenko]

Hello Björn,


MGT_CLK0_P Clock input is dedicated clock input for MGT tranceivers please look at http://www.xilinx.com/support/documentation/user_guides/ug476_7Series_Transceivers.pdf
Using this input for other purposes is not standard and requre special routing.
For internal logic you can use CLK0_P/N (pins K4/J4) clock inputs, which connected to MRCC FPGA pins.

Best regards
Oleksandr Kiyenko

[Antti Lukats]

you can use the GT clock very easily, either by using special clock buffer primitive in VHDL or then Vivado Catalog IP Core

"buffer" it has selection to choose GT buffer, then it can be used to access GT clock from the FPGA Logic

please look there

https://wiki.trenz-electronic.de/display/PD/LED+Blinky+Tutorial

I added screenshots for GT Clock access both for 7 series (TE0712) as for ultrascale devices

[bjoernr.]

Thanks for the quick reply.
Ive changed the pin to H4. (As referred in the schematic - PLL_CLK_P).
Now generation of the bitstream works without an error but if i programm the device
nothing happens.

The two LEDs from the TE0712 change from blinking to constant on. The LED D2 on the carrierboard remains constant on.

If i disconnects the power and reconnect it - D2 is still constant on and the two LEDs on the TE0712 starts blinking again.

What im doing wrong ?

[Antti Lukats]

I hope you did not forge to instantiate the Differntial buffer?

If you try to get clock from one pin from differential input, you get nothing of course, no clock.

[bjoernr.]

No i only took the _p.

Changed that and nothing happend again.

Even if i only try to turn the LEDs on without any counter the behaviour wont change.

...behav of blinki is
begin
LED1 <= '1';
LED2 <= '2';
end blinki

Do i miss any necessary things ?

[JH]

Hi,

do you watch to the correct leds?

from your xdc file, you use:

set_property PACKAGE_PIN J16 [get_ports LED1]
-> goes to the baseboard led D4 (green)
set_property PACKAGE_PIN M17 [get_ports LED2]
-> goes to the baseboard led D3 (red)

Did you have a IO-Power supply for bank 15 on? It comes from TE0703 JB2 connector (B1).

And what should be LED2 <= '2'  ; It should be LED2 <= '1';


If you used a differential  io in your vhdl-file, you can instantiate the buffer, described in:
http://www.xilinx.com/support/documentation/sw_manuals/xilinx2015_4/ug953-vivado-7series-libraries.pdf

But's easier to use vivado block-design to generate your design.

br
John

[bjoernr.]

Hey,
on the carrier board are four LEDs (D1-D4). In my VHDL file i set D3 and D4 to STD_LOGIC = 1.
The LED2 <= '2' is a typo - of course i mean LED2 <= '1'.

For now i only try to set the LEDs to constant on but as i said it wont work. What do u mean with IO Power supply ? With FPGA Pin J16 and M17 set to STD_LOGIC = 1 (IOSTANDARD LVCMOS33) the LEDs should get 3.3v and be constant on.

I generate the bitstream with no erros or warnings. Then open the Hardware manager and programm the device with my compiled blinki.bit.

Before the programming D2 (on the carrierboard) is constant on (green). The two LEDs (green and red) on the Micromodule are flashing.

After programming - D2 is still constant on and also the two LEDs on the Micromodule are constant on.

Shouldnt D3 and D4 be also constant on if the programming was successful ?

Even if i wait 10 minutes or do a power reset the LEDs do the same as before programming

Thanks for your help,
Björn

[Antti Lukats]

please open this LED Tutorial

https://wiki.trenz-electronic.de/display/PD/LED+Blinky+Tutorial

there is at the beginning a short list of requirements.

Please read item [8] list

If you are not sure about some of them or do not understand some of them then you have learn what they mean before you proceed.

You can choose and I/O standard you want, that has no impact on the actual voltage level on the output pin, if your IO output driver is powered say with 2.5V, then setting the IO Standard to 3.3V will not CHANGE YOUR POWER SUPPLY from 2.5V to 3.3V

on our micromodules the IO voltage per IO bank is made flexible so that the user, SAY YOU can choose what voltage you want. If you do not provide any voltage the IO bank may be without power, and in such case you can not turn on a LED on that bank.

[JH]

Hi,

you can use the excel pinout table to generate a B2B-Pinout table. The Bank voltage connection is displayed there too.
https://shop.trenz-electronic.de/de/Download/?path=Trenz_Electronic/Pinout

So on the carrier board TE0703 the power supply for the FPGA Bank 15 of the Module TE0712 is connected to the Pin B1 of the externel connector J2 (Bottom Side) or via Resistor R26 (Bottom Side) to 3.3V from TE0712.
Attention wrong voltages can damage the FPGA!

Here are some links that will be helpful:
https://shop.trenz-electronic.de/de/Download/?path=Trenz_Electronic/TE0712/REV02/Schematic
https://shop.trenz-electronic.de/de/Download/?path=Trenz_Electronic/carrier_boards/TE0703/documents
http://www.xilinx.com/support/documentation/data_sheets/ds181_Artix_7_Data_Sheet.pdf
http://www.xilinx.com/support/documentation/user_guides/ug471_7Series_SelectIO.pdf

br
John

[bjoernr.]

Sry but i dont get it.

My TE0712 modul ist mounted on my TE0703 carrierboard. So JM1 -> JB1 JM2 -> JB2 JM3->JB3. Shouldnt the Artix get the power trough the connectors ?

Or what exactly i have to do to get the power to the bank ?

Björn

[JH]

Hi,

you find some additional informations:
https://wiki.trenz-electronic.de/display/PD/TE0703
https://wiki.trenz-electronic.de/display/TE0712/TE0712+User+Manual

For your LED Pins on Bank 15:
Module TE0712 provides 3.3V  over some connector pins to the Carrier boards TE0703 (Modul JM2-10,JM2-12 <-->Carrier JB2.9,JB2-11), which supplies the Module Bank 15 over the connector when 0Ohm Resistor is insert on R26 (Bottom Side of the Carrier Board) (Modul JM2-7,JM2-9 <-->Carrier JB2-8,JB2-10).

Is there a 0Ohm Resistor on R26?

br
John

[bjoernr.]

No there is nothing.

But there a two free resistors R26 and R25 - do i have to set the solder bridge horizontal oder vertically ?

[JH]

Hi,

vertically (this pads which are not connected via copper near R26-Label).

br
John

[bjoernr.]

Shouldnt the solder bridge be at R25 referred to the schematic ?

Thanks for your patient but im really new to FPGA

[Antti Lukats]

You do not have to solder any 0 ohm, you can also supply the IO Voltages over the VG96 connectors:

https://wiki.trenz-electronic.de/display/PD/TE0703

there are RED wires that show how to supply VCCIO 3.3V to all banks if the connectors are not soldered.

[Antti Lukats]

Shouldnt the solder bridge be at R25 referred to the schematic ?

Thanks for your patient but im really new to FPGA

IMPORTANT: the net names on TE0703 are net names for TE0720 module, if you have TE0712, then the banks are different this may cause confusion.

[Antti Lukats]

@bjoernr

we did build a test bit file based you your constraints given and LEDS are on on TE0703+TE0712.

So it works here if we do the same as you have described.

[bjoernr.]

Solution:

TE0712 + TE0703 needs an other wiring to get 3.3V to bank 15. You have to set the jumperwire from J2.C32 - > J2.B1.
In Netnames : You apply with this jumperwire 3.3V to VCCIO13. VCCIO13 is connected to VCCIO15 on JM2 (JB2).

The way to solder a 0 ohm resistor or bridge to R26 still works either.

Thanks for patience and your help =)

[JH]

Hi,

that's same as i wrote on "Reply #9 on: June 21, 2016, 09:41:24 AM »":

So on the carrier board TE0703 the power supply for the FPGA Bank 15 of the Module TE0712 is connected to the Pin B1 of the externel connector J2 (Bottom Side) or via Resistor R26 (Bottom Side) to 3.3V from TE0712.

Or is written in our Wiki:
https://wiki.trenz-electronic.de/display/PD/TE0703


Nice, that it's working now on your system.
br
John