TE0715 and TE0701 Power Consumption

[rmd91]

Hello,

I've been using a TE07015-30 with a TE0701 and an FMC card in my design and I've noticed both that the FPGA gets rather hot (85C from XADC) and the power consumption is considerably high (about 10W at 12V DC). With the CPU in sleep and FMC card removed, the board was still drawing about 4W from the 12V supply. Please note that the main clocks in my design are sourced from the FMC card and PS IOPLL, so most clocks should be stopped in this situation.

I've downloaded the most recent pre-built test_board design and loaded that. When active, I'm measuring about 3.6W on the 12V supply. With the CPU in sleep I've only seen it reduced to about 2.9W.

Are these power numbers consistent with any of your testing? As we are targeting a portable application, we'd really like to know where we can save power.

Thank you,
Richard

[Antti Lukats]

not so surprising numbers.

thumb estimate is that with 7030 and DDR3 active it is hard to stay below 3W, no matter what you do.

TE0701 uses 5V for TE0715 DCDC supply, with 3.3V the efficiency of the on-board supplies a little bit better, but the total consumption efficiency depends on the input voltage and what DCDC have better efficiency.

There are some small things to reduce power, but they give only small improvement. With better cooling consumption goes lower too a bit.

[rmd91]

Hi Antti

Thanks for confirming that. We're in the processing of design a custom carrier board for the 7030 module. We'll be supplying the TE0715 DCDC from a 3.7V battery, so I would expect to cut on the loss from the 12V and 5V supplies on the TE0701.

In regards to the DDR, is that accounting for the self-refresh mode when the CPU is in sleep? Most of the time the CPU will be in a sleep state and only portions of the design will be active. Is there a way I can configure the memory controller to "ignore" one of the DDR chips?

In your opinion, is a "low power" application possible with this module?

Thank you,
Richard

[Antti Lukats]

next rev will have DDR3L, this saves a little bit, and optionally the module could be assembled with only 1 DDR IC, that would give a bit more savings.
you can disable the second DDR chip, but I have not made measurement how much that brings savings.

as of sleep and refresh this info is somewhere very deep in Xilinx innerworld, and may depend on zilion of things, so I would not count so much on that savings.

can you send your exact requirements for the product to support@ ?
both functional needs as actual space that is available, we can try figure out what is feasible for your application then