zynqberry tutorial for dummies

[svenssonjoel]

Is anyone up to speed with the zynqberry boards by now ?
If so. I would be extremely thankful to anyone who constructs a zynqberry version of a tutorial such as this one: http://www.fpgadeveloper.com/2014/07/creating-a-base-system-for-the-zynq-in-vivado.html

Up to this point I have been trying to get anywhere starting from the "hello_world" example. Which works fine if I program the device from the prebuilt  binaries in the package.
Recreating those however has been a dead-end (even after picking the brains of people on the Xilinx forums).

Thank you

[Shogun]

Hi svensonjoel,

up to speed? The ZPi was just released and I guess most of the sold units are in the hands of zynq beginners as we are.
It turns out it is a quite difficult task to get familiar with the zynq. We should share our experiences.

Major things I found out and some took me an enormous amount of time are:
- Trenz highly recommends to install Vivado to c:\Xilinx!
- A good place to start are the Trenz reference designs. They are good for deployment and to fulfill some tasks, but do not use them for development, the turn around times are far too slow and you do not have a debugger. Use the SDK instead!
- hdmi_fb does not work on all devices, you have a good chance if your monitor has an hdmi input. Many tv require a hdmi handshake or the screen will stay dark.
- Have a serial terminal opened before you start the flash or you will miss the uart outputs. Jtag uart and flash work in parallel!

How to create "Hello World" in SDK:
1. File/New/Application Project
   Select a default location
   Enter the project name: "Hello_World"
   Push the Hardware Platform select button [...] and in the box "Target Hardware Specification" use the "Browse"-Button to import from the test_board reference design "test_board/prebuilt/hardware/TE0726-<your board version>/test_board.hdf".
   Hardware Platform should now list "test_board_hw_platform_0" and you can immediately select that from now on.
   Hit the "Next Button"
2. Select "Hello World" from the templates.
   Hit "Finish" and wait patiently until the build is finished.
3. Now the really important! Many thanks to John Hartfield at Trenz, never I would have found that!
   In "system.mss" (should initally be opened) hit "Modify this BSP's Settings".
   Select "standalone"
   Choose "ps7_uart_1" for stdin and stdout!
   Hit OK and the project rebuilds.
4. Open a Terminal to your ZPi. I use Putty.
   In the SDK, Project Explorer, right click on "Hello_World", select "Run as/Lauch on Hardware (GDB).
   You now should see "Hello World" in your terminal and are ready to explore zynq baremetal.
I suggest next you try the "Peripheral Test" template.

This weekend I tried to get i2c working. I still use the test_board.hdf. The 40-pin connector of the board is not supported from the reference hdf's yet. But the 5 pin connector is.
I have not got that working. The experiences are typically the same I have since I got this board. There is always a show stopper, something that knocks me out. Too many questions arise, it is very time consuming to find answers (if there are any). Tutorials that you find in the net are often outdated, information that you get is misleading or wrong. Even from Xilinx.  But I feel I make some progress.
Example: For an i2c_scan I used library function XIicPs_MasterSendPolled(). Xilinx documents say there is a timeout, but it is not, the function does not return! I did not find any additional information about that.

At least some days ago I got Petalinux to work, with USB and ethernet supported. I failed to extend to an OpenAmp-system, followed the PetaLinux Setup described in UG1186 until the selection of rootfs apps and modules which are not accessible.
If there is demand on a tutorial on how to get a 2 core Petalinux working I would write that down.

For all who want to learn about PL and AXI, here are really good video tutorials from Mohammad Sadri: http://www.googoolia.com/wp/category/zynq-training/

Have fun
Mike

[svenssonjoel]

Thanks for the reply. That is actually to some degree helpful.

However, what sets the zynq apart from other systems (where I could much more easily do dual core arm programming) is the fpga.
And as it seems right now that part is totally unaccessible to me. 

It is strange though, because the person who produces the "hdmi" example and the "hello_world" clearly is able to go through
the development process (all the steps in Vivado and so on) and get something that works. While for me even the simplest attempt
turns into hundreds of critical errors (even when using the board-files provided as part of these examples). Now I am not knowledgeable enough
in Vivado to make much sense of these critical errors or how critical they are (but it does sound pretty scary, right ?)

I am also very confused about the get_ports tcl command. If used without arguments this produces a list of ports "FIXED_IO_mio

• , ... " while
  many of the critical errors seems to be related to "ports" that are not in this list. Now again I am not knowledgeable enough to make sense of that . I end up just assuming that the board-defs and presets etc supplied with the test programs are bogus and know not how to proceed.
  This I have also tried to investigate and to find answers to via Xilinx forums but no-one seems to have an appropriate answer.
  
  Thank you again for the helpful answer! It is great to hear that there are more people trying to hack and get further with this board.
  
  

[Antti Lukats]

the fixed_mio

is xilinx MESS, ignore this... CLG225 package has less DDR pins, and vivado does not know this, and the MIO pins are not actually configured by vivado at all only by FSBL.. so there is some mess

xilinx will maybe eventually clean it up

[JH]

Hi svenssonjoel,

i'm the person how create this project. 
In this case, you can ignore these critical warnings, because it's a "small mistake" from Xilinx IP Core. In the Block Design we used the Zynq Processing Modul from Xilinx (processing_system7_0). This IP-Core is written for all Zynq Processor Systems and some Zynq-FPGAs have more MIOs than the XC7010 that we have used. So the synthese and implementation steps read the general constrains files from the ip (zsys_processing7_0_0.xdc) and produced a warning for every port, that's not found.
The most IP-Cores are written very generally and dependently from the options you used, some warnings or critical warnings will be generated. It's not only a problem from Xilinx, if you work with Altera FPGAs (Software: Quartus II) or some third part programs, you have the same problem.
So in general, if you find Warnings in your own code, you should check them, if you found warning in predefined IPs, you can ignore them in the most cases. But unfortunately it's not always the case.

I hope I could help you with this answer.

BR
John

[svenssonjoel]

Awesome, with this new information at hand I will resume my experimentation.

I will surely be back with more questions. But maybe now, hopefully, also reports of success

Thanks!

[pklasa]

Can anybody help me to run openAMP for zynqBerry?

[JH]

Hi,

sorry, I didn't tried out this, so I can only send some link:

   
• http://www.wiki.xilinx.com/OpenAMP
• http://www.wiki.xilinx.com/OpenAMP+2017.1
• https://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_1/ug1186-zynq-openamp-gsg.pdf

I used 2017.1 links, because our current available board part files are 2017.1. 2017.4 will be the next update from our side.

I hope this links helps.
Best regards
John