TE0715 GPIO

[rouben_s]

I am using the TE0715 module with the TE0701 carrier card. I want to interface with the FMC connector on the carrier card but not sure how to pick the correct GPIO on the module. In Vivado I have the options J1:P1A, J1:P1B, J2:P2A, J2:P2B, J2:P2C, and J3:P3. The FMC signals that I am trying to access are located on the JM2 connector of the module. How can I specify the GPIOs that I want in the Vivado design and the .xdc? How do the J#:P# translate to the B2B connectors on the module?

[Antti Lukats]

1 as our FPGA SoMs can be used on different baseboard we can not add meaningful fixed interfaces into board part files to support all possible baseboards.
2 using FMC connector as GPIO would be meaningless in almost all cases, pretty much all FMC cards need custom IP Cores and not GPIO

please use our master excel table to create the I/O constraints for the IP Cores you want to connect to FMC

[Thorsten Trenz]

Hi,
the tables can be found here:
https://shop.trenz-electronic.de/de/Download/?path=Trenz_Electronic/Pinout

Best Regards
Thorsten Trenz

[rouben_s]

Antti,

Are you saying that I cannot assign individual bits to the FMC pins? In my application I want to drive some signals to the daughter card thru the FMC and monitor them over the header pins on the daughter card.

[Antti Lukats]

No, of course not.

you can do anything you want with the IO pins in the FMC connector.

What I said is that using GPIO - a general purpose GPIO on PS7 to control an FMC card is not meaningful in most cases, as FMC cards have usually special IC that required special IP Cores to talk to them.

If you have a pin header in FMC, or some IP core that has slow control or monitor pins, then you can assign them of course to GPIO, thats fine, but in all such cases you must prepare the pin mapping, as you are the only one whos knows what pins you want to be controlled by GPIO.

[cayla_st]

Hi,

Your Excel tool is very well designed and useful for us ... but we have designed a specific carrier board for our needs so I wonder if will be possible to adapt the tools to add our board to the "select carrier board" menu ?

Thanks
Stéphane

[jheck]

Hi,

I'm currently struggling with a simple GPIO example in the PL area as well.
I was working with zedboard before, but with the TE0715 ZYNQ 7030 Module and the 0706 Carrier-board I can't even get the simplest GPIO operation working.

My target is to set all IOs of bank 13 to HIGH to double check the pin routings of our baseboard adapter - but unfortunately this simple task  is not working for me.
- The project was created by using the TEST_BOARD script with the right board part name: trenz.biz:te0715-01-30-1c:part0:1.0
- I set up the AXI Master in the ZYNQ IP Configuration and added the AXI GPIO IP.
  But, I also can't figure out the meaning of the crypted J1:P1A, J1:P1B, J2:P2A, J2:P2B, J2:P2C, and J3:P3. combinations, which I'm able to select during the GPIO IP configuration... so I used CUSTOM.
- I set all ports of the GPIO IP as OUTPUT and "0xFFFFFFFF" as default value
- Made an external port and named it "GPIO[31:0]"
- I set up the constrains:

Code Select Expand

set_property PACKAGE_PIN W12 [get_ports {GPIO[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {GPIO[0]}]
set_property PACKAGE_PIN U17 [get_ports {GPIO[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {GPIO[1]}]
...
set_property PACKAGE_PIN U19 [get_ports {GPIO[31]}]
set_property IOSTANDARD LVCMOS33 [get_ports {GPIO[31]}]

- To ensure all ports are really set to "1" I also manually set the GPIO[31:0] in the wrapper hdl file to "0xFFFFFFFF"
   => VIVADO quits this with a notification that all GPIO output ports are constant driven by "1" which is correct.
- Synthesis and implementation run without any error: Just the few "more than one IO STANDARD" (DRC-23-20) messages which can be ignored.
- Programmed the device but not one of the specified outputs is driving HIGH.

What am I doing wrong?
Maybe the DIP switches of the XMOD JTAG Adapter or the Baseboard is not set correctly (I'cant find a documentation regarding these switches...)

Thanks in advanced and regards
Joachim

[Antti Lukats]

Hi,

I'm currently struggling with a simple GPIO example in the PL area as well.
I was working with zedboard before, but with the TE0715 ZYNQ 7030 Module and the 0706 Carrier-board I can't even get the simplest GPIO operation working.

My target is to set all IOs of bank 13 to HIGH to double check the pin routings of our baseboard adapter - but unfortunately this simple task  is not working for me.
- The project was created by using the TEST_BOARD script with the right board part name: trenz.biz:te0715-01-30-1c:part0:1.0
- I set up the AXI Master in the ZYNQ IP Configuration and added the AXI GPIO IP.
  But, I also can't figure out the meaning of the crypted J1:P1A, J1:P1B, J2:P2A, J2:P2B, J2:P2C, and J3:P3. combinations, which I'm able to select during the GPIO IP configuration... so I used CUSTOM.
- I set all ports of the GPIO IP as OUTPUT and "0xFFFFFFFF" as default value
- Made an external port and named it "GPIO[31:0]"
- I set up the constrains:

Code Select Expand

set_property PACKAGE_PIN W12 [get_ports {GPIO[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {GPIO[0]}]
set_property PACKAGE_PIN U17 [get_ports {GPIO[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {GPIO[1]}]
...
set_property PACKAGE_PIN U19 [get_ports {GPIO[31]}]
set_property IOSTANDARD LVCMOS33 [get_ports {GPIO[31]}]

- To ensure all ports are really set to "1" I also manually set the GPIO[31:0] in the wrapper hdl file to "0xFFFFFFFF"
   => VIVADO quits this with a notification that all GPIO output ports are constant driven by "1" which is correct.
- Synthesis and implementation run without any error: Just the few "more than one IO STANDARD" (DRC-23-20) messages which can be ignored.
- Programmed the device but not one of the specified outputs is driving HIGH.

What am I doing wrong?
Maybe the DIP switches of the XMOD JTAG Adapter or the Baseboard is not set correctly (I'cant find a documentation regarding these switches...)

Thanks in advanced and regards
Joachim

Hi

https://wiki.trenz-electronic.de/display/PD/LED+Blinky+Tutorial

I will add there more helpful information, LED blinky task is very similar to the GPIO task.

if you have not supplied valid I/O voltage to any banks of the TE0715, then on TE0706 all banks will be without VCCIO, so everything maybe just works, but you do not see it as the FPGA output drivers have power.

[jheck]

Hi Antti Lukats, thanks for your fast reply. 

- Do you mean, that I have to provide the VCCIO_B13_IN at some point manually?
  I thought, that this is already handled by the TE0706 Baseboard.

- Or that there must be 3v3 selected as IOSTANDARD via VIVADO?
  This is what I already done via the constaints file.

I checked the block design and see all PL-PS clocks are connected.

[Antti Lukats]

Hi Antti Lukats, thanks for your fast reply. 

- Do you mean, that I have to provide the VCCIO_B13_IN at some point manually?
  I thought, that this is already handled by the TE0706 Baseboard.

- Or that there must be 3v3 selected as IOSTANDARD via VIVADO?
  This is what I already done via the constaints file.

I checked the block design and see all PL-PS clocks are connected.

You can select any IOSTANDARD in Vivado, but this settings can of course not implement a physical connection, or change the voltage of external supplies.
The IOSTANDARD only "fine tunes the IOB properties", the bank voltage must be correct and externally supplied for any selected IOSTANDARD you want to use.

for LVCMOS33, VCCIO must be 3.3V this is all explained in Xilinx documentation

**
As we do not know in advance what VCCIO our customer needs, we provide the option to supply those voltage to the Customer.

https://wiki.trenz-electronic.de/display/PD/TE0706

There is one bank that support 3.3V

[jheck]

Ough,... now I seem to get it! Thanks for the attached link.

If I'm interpreting the second section right:
With standard delivery of the TE0706, TE0715 would have all 3 FPGA I/O Banks not powered.

TE0706 with TE0715-30

B13	3.3	JB1.10 JB.12	B32	Can solder R20 to use 3.3V in TE0715 bank B13
B34	1.8V	JB2.6	-	Must be connected with fly wire on TE0706, not accessible on the connector
B35	1.8V	JB2.8 /JB2.10	B1	Must connect 1.8V max either wire or from VG96 connector

It seems like my IO-Banks are not powered! In Order to get it working i need to:
1. Shorten R20    => B13 gets 3v3
    => But this doesn't fit to the schematic of TE0706 Page 2: http://www.trenz-electronic.de/fileadmin/docs/Trenz_Electronic/carrier_boards/TE0706/documents/SCH-TE0706-01.PDF
    => This says in order to power B13 I need to shorten R22 = VCIO13
    => Shortening R20 would blow up VCCIO35 which only accepts 1v8
So, which one is the right one?

2. I'm not sure how to proceed with the other two banks either.... Flywire?

Thanks so much for your support!
Regards, Joachim!

[Antti Lukats]

Ough,... now I seem to get it! Thanks for the attached link.

If I'm interpreting the second section right:
With standard delivery of the TE0706, TE0715 would have all 3 FPGA I/O Banks not powered.
It seems like my IO-Banks are not powered! In Order to get it working i need to:
1. Shorten R20    => B13 gets 3v3
    => But this doesn't fit to the schematic of TE0706 Page 2: http://www.trenz-electronic.de/fileadmin/docs/Trenz_Electronic/carrier_boards/TE0706/documents/SCH-TE0706-01.PDF
    => This says in order to power B13 I need to shorten R22 = VCIO13
    => Shortening R20 would blow up VCCIO35 which only accepts 1v8
So, which one is the right one?

2. I'm not sure how to proceed with the other two banks either.... Flywire?

Thanks so much for your support!
Regards, Joachim!

TE0706 was made for TE0720 and has IO bank net names from TE0720, the bank placement and all netname of TE0715 are different, so this may make confusion, you can only use connector numbers when mapping the signals.

[jheck]

OK, perfect - its now working like a charm.
Thanks for your support!