TE0320 in combination with Altium (summer 09) problems

[rsam70]

Hi all,

we have an TE0320 board (Spartan 3A-DSP , XC3SD1800A) which we want to program via the ALTIUM (summer 09), Xilinx (12.1) toolchain.  We use an open-bus project template
(with a softcore TSK3000) and several peripherals (UART,SPI, etc)

Symptoms:
We encountered several problems with this setup (for instance):
- uart functionality unstable. Behaviour cannot be predicted. When we put an extra IO-port in the design, then the  for some reasons the TX will be enabled. RX never worked.
- An additional component introduction in the design will result unstable behaviour (some things seem to work, other components are silenced)

With the Altium Demo Nanoboard and same FPGA the project works out-of the-box.

Did anyone have this same/similar experience with this setup? If so what were the follow-up actions.

Thanks in advance.

Best Regards,

Ruud Sampers.

[Thorsten Trenz]

Hi,

Symptoms:
We encountered several problems with this setup (for instance):
- uart functionality unstable. Behaviour cannot be predicted. When we put an extra IO-port in the design, then the  for some reasons the TX will be enabled. RX never worked.
- An additional component introduction in the design will result unstable behaviour (some things seem to work, other components are silenced)

Your description looks like timing related. I do not know the FPGA section of Altium Designer, so I can't be really helpful here, but your symptoms look like some timing or IO pin problem.
Please check the following points:

   
• Are all clocks constrained correctly?
• Are all IO pins constrained correctly, even the ones you did not use in your design?
• Is the unused periphery properly deactivated, for example the DDR Ram disabled?
• Any open inputs?

best regards
Thorsten Trenz

[Ales Gorkic]

Dear Ruud,

We all use Altium Designer, but I have never composed the FPGA system with it (although I have NanoBoard 3000).
The problems you describe might be a cause of:
- timing problem (see the Xilinx implementation log - PAR report)
- inadequate power supply or incorrect grounding.
- Altium designer bug
- try putting all unused pins to tristate (Xilinx Bitgen option: -g UnusedPin:PULLNONE)

I am sorry that we cannot help you much on this issue. I hope this answers will lead you to some solution. If you have any additional question do not hesitate to ask.
We are also curious about your experience with TE modules and Altium Designer. Any example projects are also more than welcome.

Best regards,

Ales

[Arthur Ketels]

The problem with the combination Altium Designer and the TE0320 has been found. Setting the FPGA mode bits with the dipswitch on the module to have the FPGA wait for JTAG instead of downloading the bitfile from flash does the trick. Someway the default bitfile configures the FPGA in such a way it will not be reset properly by the AD tools. Thus leading to strange behavior for projects made with AD.

After setting the dipswitch, all AD generated FPGA projects seem to run fine. When I have some more time I'll make a sample project for the TE0320 / TE0323 combination and post it here.