TE0715-30 on TE0701 Carrier - FMC Lane Polarity Problems

[chris_muc]

We are using the TE0720 FPGA board on the TE0701 carrier to access an FMC card (FMCOMMS2), which works fine.
Now we try to migrate out project to an TE0715-30 FPGA board to have more FPGA resources available, but there seems to be an issue with the polarity of the differential signal lanes:

23 of those lanes have reversed polarity, i.e. FMC_LAx_P of the FMC socket is connected with the Bx_Ly_N pin of the FPGA. This leads to unplaceable I/O buffers...

[Oleksandr Kiyenko]

Hello,

You need to define reverse polarity in your xdc file to instantiate differential buffers (swap *_P and *_N pins for those signals) and then logicaly invert signals after differential buffer.

Best regards
Oleksandr Kiyenko

[chris_muc]

Thanks for providing this workaround!

For my particular case I found a simpler solution: The AD9361 chip on the FMCOMMS2 FMC card has configuration registers (0x03D, 0x03E) that allow swapping each individual differential pair at the chip.

[rmd91]

Hello Chris,

I'm planning to use these two boards as well, but I ran into an issue with the supported IO standards running the IO banks at the required 1.8V on the TX and RX LVDS data lines over the FMC connector. Were you able to find a workaround for this, or do I need to use the TE0720 board,which to my knowledge doesn't have this restriction?

Thank you,
Richard

[Antti Lukats]

Hi

what exact problem are you facíng ?

LVDS is supported in HP banks at 1.8V no issues using LVDS.

[chris_muc]

Hi rmd91,

This works perfectly fine now with the TE0715 board.
To avoid the problem with the I/O-standard, I have configured the IOs as "LVDS_25" with "DIFF_TERM TRUE".
The bank itself is just powered with 1.8 V, which is also the I/O voltage of the AD9361 chip on the FMC card.
I checked the signals on the differential lines with an oscilloscope and they look good with this configuration.

You can contact me directly (christoph.heller@airbus.com) if you need further information on this.

Best regards,
Christoph

[rmd91]

Hi Christoph,

I constrained those to LVDS_25 as well to get through the placer, but I was concerned it wouldn't work on the board. I glad to hear that this configuration works. I'll give it try with my system.

Thank you, I appreciate your reply!
Richard

[Antti Lukats]

this is confusing, but LVDS is really ok HP banks, that are 1.8V that is all documented in Xilinx datasheets.