Author Topic: TE0720 reference design - DDR delays  (Read 2669 times)

Ced

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TE0720 reference design - DDR delays
« on: July 17, 2015, 10:19:17 AM »
Hello,
I'm using the TE0720 with Vivado 2014.4.
According to the wiki the delays for the DDR must not be left to 0  (https://wiki.trenz-electronic.de/pages/viewpage.action?pageId=10625459).
The correct delay values have to be loaded from the file "TE0720-01_a.xml":
  <set param="PCW::UIPARAM::DDR::DQS_TO_CLK_DELAY_0" value="0.143" />
  <set param="PCW::UIPARAM::DDR::DQS_TO_CLK_DELAY_1" value="0.148" />
  <set param="PCW::UIPARAM::DDR::DQS_TO_CLK_DELAY_2" value="0.203" />
  <set param="PCW::UIPARAM::DDR::DQS_TO_CLK_DELAY_3" value="0.225" />
  <set param="PCW::UIPARAM::DDR::BOARD_DELAY0" value="0.156" />
  <set param="PCW::UIPARAM::DDR::BOARD_DELAY1" value="0.154" />
  <set param="PCW::UIPARAM::DDR::BOARD_DELAY2" value="0.199" />
  <set param="PCW::UIPARAM::DDR::BOARD_DELAY3" value="0.188" />


1. After creating a new project based on the Board "TE0720-2EF" the DDR delays are all '0'. I was actually expecting the delays to be part of the Board File.

2. Looking into the Board files "TE0720-2EF" I found some delays defined in the "PS7.tcl" file, but they are completely different from the above ones (-0.001 / -0.002 / -0.001 / -0.008 / 0.010 / 0.010 / 0.010 / 0.013).
Why are they different, why aren't they taken in account ?

3. In the reference designs (e.g. TE0720-02-hdmi or TE0701_hdmi_tpg) the delays are also left to 0, they are not overwritten.

Can you please give me a step-by-step information how I have to deal with those delays ?
Are there some other settings which need to be overwritten ?

Thanks and regards,
C├ędric

PS: I'm using now 2014.4 but will switch soon to 2015.2