TE0701-03 with TE0720-01 - JTAG debugging with Lauterbach Debugger

[MichaelR]

Hi,

I'm working with trenz board for first time and try to debug with Lauterbach Power Debug Pro over JTAG.
I don't use xilinx toolchain.
If I try to detect the JTAG with Lauterbach Toolchain I get error "Could not set JtagClock".

I connect the debugger over J15 and I didn't use any FPGA config.
So I checked the level of JTAG pins at J15 and found out that the levels are wrong (e.g. pin 1 VREF is < 2V instead of 3.3V)
The question is, are the JTAG signals routed to J15 by default or do I need a bitstream for the FPGA.

thanks

best regards   

[Antti Lukats]

J15 is connected to FPGA PL IO pins only, and is usable if:

1 Zynq on TE0720 is configured to boot in "separate chain mode"
2 Zynq has booted FSBL and that FSBL has configure the JTAG MIO-EMIO multiplexing
3 Bitstream is loaded that connects ARM JTAG via EMIO and PL fabric to J15

TE0720 standard configuration does NOT support separate JTAG mode, CASCADED mode is used by default, and that case the main JTAG chain with FPGA and ARM is connected to TE0701 FT2232H channel A.

Please send us email to support if you really want to have access  to the ARM DAP in separated jtag chain mode.