when creating bitstream for TE0300_v1.0.1.2 error is coming

[pv1984]

 I have xilinx edk and ise 9.2i versions. the project TE0300_v1.0.1.2 has a system file i double click it . it updates the microblaxe version from 7.00b to 7.00a. then i run create netlist .the netlist process is error free. but when i click generate bit stream it gives the following error


NgdBuild:604 - logical block
   'xps_fx2_0/xps_fx2_0/USER_LOGIC_I/CORE_IMPLEMENTATION/TX_FIFI' with type
   'tx_fifo' could not be resolved. A pin name misspelling can cause this, a
   missing edif or ngc file, or the misspelling of a type name. Symbol 'tx_fifo'
   is not supported in target 'spartan3e'.

please help

[Horsa]

Dear pv1984,
thank you for contacting us.

It seems, your XPS cannot find the following file:
"...\TE0300_v1.0.1.2\pcores\xps_fx2_v1_00_a\devl\projnav\tx_fifo.xco"
I assume you cannot use any newer ISE versions, what prevents you from using our corresponding newer reference designs and us from supporting you to the best possible extent. ISE 9 is almost 4 years old now.

Please tell us your module hardware revision ("TE0300-0x" string) printed on the top side between the push-button and connector J2.
Then there are some general hints always useful for Xilinx ISE:
- do not allow spaces in the installation path or project/source path
- try "Project > clean all generated files", then retry from start
If it still fails, can you retry on another computer?

[Ales Gorkic]

Dear pv,

It seems that the FIFO core tx_fifo.ngc was not created.
Can you please post a coregen log:
implementation\xps_fx2_0_wrapper\*.log

If an error happened then it should have been documented.

The  xps_fx2 core uses TCL script (xps_fx2_v2_1_0.tcl) to generate TX_FIFO on the fly. Maybe your version of tools does not support this version of Coregen Fifo generator.

Best regards,

Ales

[pv1984]

hi ales/horsa

  thanks for replying.... yes there is an error in generating the fifo .the following is documented:

**********************************************************
* xps_fx2_0
**********************************************************
xps_fx2_0 : Running Core Generator to generate FIFOs. . .
xps_fx2_0: ERROR FIFO Core Generation Failed

please help.

[Horsa]

First of all,

microblaxe version from 7.00b to 7.00a

is by no means an upgrade, but rather a DOWNgrade. That is already very suspicious and should be investigated.

Did you installed the latest ISE 9 service pack (ISE Foundation - 9.2i Service Pack 4)? In particular for EDK?
    http://www.xilinx.com/support/download/index.htm
    http://www.xilinx.com/csi/dlc-tab-archive.htm
    http://www.xilinx.com/support/answers/25384.htm

Please execute common\bin\nt\xinfo.exe in your Xilinx folder, expport  the results and send us your file.

Moreover, you forgot to provide information required by us to support you:

• Please tell us your module hardware revision ("TE0300-0x" string) printed on the top side between the push-button and connector J2. Alternatively send us your serial number
• please post a coregen log:
  implementation\xps_fx2_0_wrapper\*.log