Secondary UART from TE0720 sems not to be relayed though CPLD to VG96 connector

[DrFluteDos]

I have a bare metal application running on a SoM TE0720 that pushes messages out to both PS uarts and also to PL axilite uart. I can receive these messages on my development PC from PS uart0, and PL axilite uart, but not PS uart1. According to the TE0703 carrier TRM (see attached image), the SoM uart1 Tx and Rx lines (nets MIO12, MIO13) pass through the carrier CPLD and onto the VG96 connector (nets X16 and X17). However, there is a suggestion that this is CPLD firmware dependent. I've download the CPLD source code and it seems fine. However, I can't tell what version of CPLD code is actually currently running.

Can you help please.

Kind regards
   
   
 

[JH]

Hi,
did you checked that TX/RX is maybe swapped. X17 should be TX and X16 RX (view from FPGA)?
Did you you try a simple design with only uart1, maybe it's some driver issue for multiple uart?
Which vivado version did you use?
Can you tell me the serial number of the carrier and the module. It's the number of the smaal sticker with QR code.

br
John