TE0720-04-61C33MA: ps7_init fails on custom carrier, DDR cannot be initialized

[Keisuke Sakai]

Hi,

I am using a TE0720-04-61C33MA SOM with Vivado/Vitis 2024.2.
(Using "TE0720-te0720-rd-vivado_2024.2-build_1_20250618151152.zip")

The same SOM, the same hardware design, and the same ps7_init.tcl are tested on:

- TE0703 carrier board (working)
- Custom carrier board via Platform Cable USB II (failing)

JTAG access is working on both boards.

Both ARM Cortex-A9 cores are visible in XSCT and can be stopped successfully. However, DDR memory cannot be accessed on the custom carrier, as shown in the logs below.

-------------------------------------------------------
TE0720 configuration-related pins on my custom carrier:
-------------------------------------------------------

- JTAGMODE (JM1-89): GND
- NOSEQ (JM1-7): GND
- MODE (JM1-32): 3.3 V
- PGOOD (JM1-30): Open
- EN1 (JM1-28): 3.3 V
- MIO0 (JM1-87): Open

--------------------------------------------------
On TE0703 (Working)
--------------------------------------------------

connect
targets
targets -set -filter {name =~ "APU"}
stop
targets -set -filter {name =~ "ARM Cortex-A9 MPCore #0"}

mrd 0xF8000B40
F8000B40: 00000800

mrd 0xF8000B44
F8000B44: 00000800

mrd 0x00100000
Memory read error at 0x100000.
Cannot access DDR: the controller is held in reset

source {C:/TE0720-te0720-rd-vivado_2024.2-build_1_20250618151152/te0720-rd/vivado/vitis/zsys_plat/hw/ps7_init.tcl}

ps7_init

mrd 0xF8000B40
F8000B40: 00000600

mrd 0xF8000B44
F8000B44: 00000600

mrd 0x00100000
100000: F7EFEFFF

--------------------------------------------------
On Custom Carrier (Failing)
--------------------------------------------------

connect
targets
targets -set -filter {name =~ "APU"}
stop
targets -set -filter {name =~ "ARM Cortex-A9 MPCore #0"}

mrd 0xF8000B40
F8000B40: 00000800

mrd 0xF8000B44
F8000B44: 00000800

mrd 0x00100000
Memory read error at 0x100000.
Cannot access DDR: the controller is held in reset

source {C:/TE0720-te0720-rd-vivado_2024.2-build_1_20250618151152/te0720-rd/vivado/vitis/zsys_plat/hw/ps7_init.tcl}

ps7_init

Memory read error at 0xF8000B44.
Invalid DAP IDCODE 00000000.
Invalid DAP ACK value: 0

mrd 0xF8000B40
F8000B40: 00000800

mrd 0xF8000B44
F8000B44: 00000800

mrd 0x00100000
Memory read error at 0x100000.
Cannot access DDR: the controller is held in reset

--------------------------------------------------

The same SOM, the same Vivado/Vitis version, and the same ps7_init.tcl work correctly on the TE0703 carrier board, but ps7_init fails on the custom carrier before DDR initialization completes.

Besides hardware-related causes, are there any software settings, configuration options, or debugging approaches that could help identify or resolve this issue?

Any suggestions for further investigation would be greatly appreciated.

Kind regards,
K. Sakai

[Keisuke Sakai]

Additional information:

I also tested the same TE0720 module with a TEBA0841-02 carrier board.

On the TEBA0841-02, ps7_init completes without any errors and the values of 0xF8000B40 and 0xF8000B44 change from 0x00000800 to 0x00000600, similarly to the behavior observed on the TE0703.

However, DDR still cannot be accessed afterwards:

--------------------------------------------------
On TEBA0841-02 (Failing)
--------------------------------------------------

mrd 0xF8000B40
F8000B40: 00000800

mrd 0xF8000B44
F8000B44: 00000800

mrd 0x00100000
Memory read error at 0x100000.
Cannot access DDR: the controller is held in reset

source {ps7_init.tcl}

ps7_init

mrd 0xF8000B40
F8000B40: 00000600

mrd 0xF8000B44
F8000B44: 00000600

mrd 0x00100000
Memory read error at 0x100000.
Cannot access DDR: the controller is held in reset

--------------------------------------------------

Therefore, there appear to be three different behaviors:

1. TE0703:
   - ps7_init succeeds
   - DDR becomes accessible

2. TEBA0841-02:
   - ps7_init succeeds
   - DDR remains inaccessible

3. Custom carrier:
   - ps7_init itself fails with
     "Invalid DAP IDCODE 00000000"

Since TEBA0841-02 is essentially a power-supply carrier, it seems possible that some boot-stage initialization (for example FSBL-related initialization) is not being executed. Could this explain why DDR remains in reset even though ps7_init completes successfully?

Kind regards,
K. Sakai