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MCB Placement error

Started by razi marjani, October 20, 2013, 02:22:08 PM

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razi marjani

HI
I've used TE0600-GigaBee_XC6LX-Axi-EDK-13.2-v1.0.f79134d.zip as a start point for my project and it works fine.
Then I added My custom IP and I tried to generate bitstream.
But I encountered whit this error.

ERROR:Place - ConstraintResolved NO placeable site for
   MCB1_DDR3/MCB1_DDR3/mcb_ui_top_0/gen_spartan6_bufpll_mcb.bufpll_0
ERROR:Place - ConstraintResolved NO placeable site for
   MCB3_DDR3/MCB3_DDR3/mcb_ui_top_0/gen_spartan6_bufpll_mcb.bufpll_0
ERROR:Place:1172 - The BUFLL/BUFPLL_MCB instance
   <MCB1_DDR3/MCB1_DDR3/mcb_ui_top_0/gen_spartan6_bufpll_mcb.bufpll_0> needs to
   have all of its IOB loads placed into its same IO bank. However, due to
   user-specified constraints, the BUFLL/BUFPLL_MCB instance
   <MCB1_DDR3/MCB1_DDR3/mcb_ui_top_0/gen_spartan6_bufpll_mcb.bufpll_0> and its
   IOB load <axi_s6_ddrx_0_mcbx_dram_dqs> cannot be placed in the same IO bank.
   These constraints could be LOCATION or AREA constraints on
   <MCB1_DDR3/MCB1_DDR3/mcb_ui_top_0/gen_spartan6_bufpll_mcb.bufpll_0>, or
   <axi_s6_ddrx_0_mcbx_dram_dqs>, or other components connected to them, which
   could impose an implicit constraint on them. Please check user-specified
   constraints on all of these components to ensure their combination is not
   infeasible.
ERROR:Place:1172 - The BUFLL/BUFPLL_MCB instance
   <MCB3_DDR3/MCB3_DDR3/mcb_ui_top_0/gen_spartan6_bufpll_mcb.bufpll_0> needs to
   have all of its IOB loads placed into its same IO bank. However, due to
   user-specified constraints, the BUFLL/BUFPLL_MCB instance
   <MCB3_DDR3/MCB3_DDR3/mcb_ui_top_0/gen_spartan6_bufpll_mcb.bufpll_0> and its
   IOB load <mcbx_dram_dqs> cannot be placed in the same IO bank. These
   constraints could be LOCATION or AREA constraints on
   <MCB3_DDR3/MCB3_DDR3/mcb_ui_top_0/gen_spartan6_bufpll_mcb.bufpll_0>, or
   <mcbx_dram_dqs>, or other components connected to them, which could impose an
   implicit constraint on them. Please check user-specified constraints on all
   of these components to ensure their combination is not infeasible.
ERROR:Xflow - Program map returned error code -1073741819. Aborting flow
   execution...
make: *** [__xps/system_routed] Error 1

I attach my mhs after adding my IP

Oleksandr Kiyenko

Hello Razi,

In your project you use additional clock generator which take more clock buffers than exist in FPGA.
Please read http://www.xilinx.com/support/documentation/user_guides/ug382.pdf and plan your clocking resources correct way.

Best regards
Oleksandr Kiyenko