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TE0720 System Controller

Started by avignani, August 05, 2013, 06:28:03 PM

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I found some disagreement between the TE0720 manual on this site and the Reference Design concerning the function of the X0-X7 lines that go from the FPGA to the System Controller. In particular, the manual seems to be outdated, because the Reference Design works as intended on my TE0720-1CF board.
The manual doesn't define the functions of X0 and X7, and places the I2C bus on the X1-X3 lines, while in your example X0 is a GPIO line that switches between accelerometer and magnetometer and the I2C bus is on X1,X5 and X7. Only X1 stays the same in both cases.
This is probably due to a revision of the CPLD firmware.
Could someone please explain what are the current functions of these X0-X7 lines (and the frequency of XCLK too, which I could not find anywhere)?


Antti Lukats


the function of those pins CPLD<>FPGA fabric are indeed defined by the CPLD version - 3 pins are used as I2C interface, that should normally be connected to Zynq PS I2C1 hard core muxed via EMIO, so that the CPLD connected I2C bus comes visible for ARM.

XCLK is connected in default CPLD config to Ethernet PHY CLK125 output, this should be 125MHz clock from clockin+PLL or recovered clock from network in case PHY is reconfigured for Sync Ethernet mode.

I will update the documents on the usage of those IO pins.



It is possible to update Wiki
according to schematic and UCF file?
Actually, X0 (I2CMUX), X1 (CLK), X5 (MISO), X7 (MOSI) pin are used for I2C-like protocol but I would like to know which pins are connected to ethernet phy leds.


Antti Lukats


all PHY LED pins are by default forwarded to FPGA IO pins, I will update documentation shortly on actual pin numbers used