[TE0950] QSFP help

[hw-lab]

Good evening all!

Recently at my office we bought two TE0950 dev boards.
At the moment we have successfully built the reference design with Petelinux and Vivado 2024.2.
Now, starting from the ref. des.,  we want to explore the QSFP interface by using the Ethernet Subsystem IP configured at 10 Gbps and use it by means of Petalinux. The idea is to start with the reference design of the Eth Subsystem and integrate it with the TE0950 reference design by means of an AXI Smart Connect.
Is there some advice that we have to follow in terms of clock configuration and/or the Artix FPGA design?
Thanks in advance,
Antonio

[M Kirberg]

Hi,

the reference design already includes an AxiSmart Connect design for Artix.

Regarding QSFP and the Artix: is it that you want to use the Control Signals and/or I2C?

I2C is already wired, the control signals could be used by wiring them to an GPIO Controller similar what is already done for Cruvi Signals.

br
Markus Kirberg

[hw-lab]

Good morning Markus.

From our understanding, the i2c configuration is completely optional, so we are ignoring it for now. Please correct me if I'm wrong.
However we would like to know if the remaining QSFP+ management signals (nRESET, nMODSEL, LPMODE) have to be driven to a specific value.
- Do we need to set LPMODE to some precise value? We already tried setting it to '0' with a quick modification to the Artix design, without success.
- We know that nRESET has a pull-up resistor inside the cable/QSFP+ module, so driving it is optional.
- We know that nMODSEL is auxiliary for the i2c bus (works like a chip select), but we are not using the i2c bus.

Here is a not-so-brief summary of what we are doing:
We are connecting the TE0950-03 board to an ethernet/SFP+ switch using this passive cable: https://it.rs-online.com/web/p/connettori-io-ad-innesto/1881446

We are using the Xilinx XXV ethernet core with DMA to PS memory, together with the Xilinx ethernet driver included in Petalinux. The interface shows up in linux as eth0, we are able to assign an address and bring up the interface, but the ethernet/SFP+ switch does not detect the link.
The SFP+ slots of the switch were tested and are all working correctly.

Linux commands:
   sudo ip link set dev eth0 up
   sudo ip addr add 10.1.1.1/24 dev eth0

The following error appears in the boot log, and every time we bring up the interface:
   [time] xilinx_axienet 80000000.ethernet eth0: XXV MAC block lock not complete! Cross-check the MAC ref clock configuration
We found other boot logs of example projects on the internet, where this error appears, but the 25G connection works without issues.
Also, the Xilinx FAE we contacted thinks this is more like a warning, and should not prevent the XXV MAC from working.

After trying to ping another address on the subnet, ifconfig shows:
   ...
   UP BROADCAST RUNNING MTU:1500 Metric:1
   RX packets:0 errors:0 dropped:0 overruns:0 frame:0
   TX packets:92 errors:0 dropped:0 overruns:0 frame:0
   ...

Thank you for your time, have a nice day

[M Kirberg]

Hi,

we have no experience with this core or application, but a non locking core warning does not sound good to me. What frequency did you set?

Regarding the additional signals, I also would say optional/default level is good enough for you. However to be sure measure the QSFP_RESET voltage on R73 as a double check.

br