TE0813 Power Sequencing using Hardware circuit without CPLD

[Rudraksh]

Hi all,

We are working with the TE0813 module and would like to implement the required power sequencing using a discrete hardware circuit instead of the onboard CPLD.

Has anyone attempted this approach, or are there any recommended reference circuits or guidelines for managing the TE0813's power rails externally (e.g., VCCIO, VCCINT, VCCAUX, etc.)?

Any insights, application notes, or experience on safely handling this sequencing externally would be greatly appreciated.

Thanks in advance!

Best regards,
Rudraksh

[Ivan7681]

According to DS925 (v1.28), page 17, the AMD MPSoC requires a specific power-up sequence. This power-up sequence is already implemented in the power architecture of the TE0813 module. If you do not need the ability to disable the PL, PS, or other functional blocks, it is sufficient to supply power to LP_DCDC, 3.3VIN, DCDC_IN, PL_DCIN, and GT_DCDC, and to connect pull-up resistors to the signals EN_LPD, EN_FPD, EN_DDR, EN_PSGT, EN_PL, and EN_GT_R.

More detailed information can be found in the TRM. It is also recommended to study the schematic SCH-TE0813-02, where you can find a detailed Power Diagram.

[jmats]

I'm running into the same issue (or at least, trying to accomplish the same thing in a custom carrier board) as Rudraksh.

Had a look through the flow chart on the wiki page on the CPLD sequencing of the TEBF0818.
Abstractifying the TEBF0818 signals to the general ones (that the TE0813 cares about), my takeaway is that the following simplified sequencing can be implemented:

• Provide carrier-level 3V3 supply + board supply PowerGood (either as a pull-up or from the carrier board power supply/converter
• Provide EN_LPD (pull-up or from the 3V3 carrier board power supply too)
• Provide EN_FPD, wired from the PG_LPD pin
• Provide EN_DDR + EN_PSGTR + EN_PLL_PWR, all wired from the PG_FPD pin
• Provide EN_PL + EN_GTR_R + EN_GTR_L, all from pull-up or the 3V3 carrier board power supply
• Once PG status has been achieved from all the Enables in steps 4 and 5, activate 1V8 supply on the carrier board for the peripherals
• Activate 3V3 supply for the carrier board peripherals + the power converter for the VCCO voltages (ie: the J4 Vref/FMC_VADJ)

Notes:

• As mentioned several times in the TRM, the PS and PL of the Ultrascale+ can be sequenced separately, so you can do steps 2-4 (PS) in parallel to step 5 (PL)
• On step 6, I imagine you need some sort of logic with transistors/basic ICs to AND operate on all these PG signals

That said, I have the following questions, and it would be great if a Trenz member (or someone who already accomplished this power sequencing in hardware) could pitch in and confirm/correct this sequencing list:

• On step 4, I see the CPLD flowchart using an EN_PLL_PWR signal (on the TEBF0818 carrier side), but in the TE0813 SoM schematics, the pin in the SoM side is tied to GND. Doesn't that make this signal redundant in the power sequencing since it's routed nowhere? Can it be ignored?
• On step 5, I was initially under the impression that you needed to activate EN_PL first, and that once you had PG_PL signal from there you can activate the EN_GTR_R/L, but from the flowchart it seems you activate it all at once. Can you confirm that this is the case? In my carrier board design, I enable EN_PL with a carrier 3V3 pull-up and route PG_PL to EN_GTR_R/L, is that acceptable too?
• On step 5 too, if I don't have need for eg: the GTR functionality, can I just forego enabling those pins, and have the SoM start up correctly regardless?
• On step 6, my carrier board is designed to bring out 1V8 from the SoM's internal converter, and use that to power my 1V8 peripherals. Is that ok? If so, does that mean I can forego this step 6 (since I don't have a 1V8 converter on my carrier board)
• On step 7, for my carrier board 3V3 peripherals I'm using the standard 3V3 power net on my carrier (aka the one that powers the SoM in step 1), and I have the VCCO voltage converters automatically enabled as soon as I have 3V3 on my carrier. In this case I essentially am not implementing step 7. Is this ok or is there a problem with supplying Vref to the VCCO reference voltages before the SoM has finished its power sequencing?

[jmats]

Below is the power-sequencing approach implemented on my v1 TE0813 custom carrier board:

• 3V3 from carrier provided directly to 3.3VIN + PL_DCIN + DCDCIN + LP_DCDC + GT_DCDC pins. As soon as the carrier is powered externally, this is activated
• 1V2 from carrier (down-converted from 3V3) provided directly to VREF pins of VCCO
• 1V8 is sourced from the PS_1V8 pins on the SoM (NO 1V8 converter on the carrier), and fed through the carrier back into the VCCO supplies, as well as some carrier board peripherals (there are some ADCs and DACs on the carrier)

The following sequencing is implemented:

• (3V3 pull-up) EN_PL
• (3V3 pull-up) EN_LPD
• SOM_LP_GD => EN_FPD
• SOM_FP_GD => EN_DDR
• SOM_DDR_GD => EN_PSGT (the PG_PSGT signal is not routed anywhere) and SOM_DDR_GD => EN_GT_R

However, in testing this sequencing does not seem to work. In the Vivado Hardware Manager, the SoM is recognised when the carrier is powered up but I am unable to program my PL. In the target device window it says that the PL is not programmed and I get the following error:

[Labtools 27-3421] xczu2_0 PL Power Status OFF, cannot connect PL TAP. Check POR_B signal.

Now, it could be a carrier board supply under-current situation (ran into this problem in earlier tests when attempting to program/flash the configuration memory and the SoM drew more current than expected), but it feels like the PL is simply not booting up to a ready status. There is also the mistake I did in step 5, where the PL GTR_R is being enabled by the PS DDR. But since the PL is being enabled separately (and at the same time as the LPD), I assume this could be fine since the GTR_R is being enabled after the PL?

Another thing done in my test rig is having an external 1V8 power supply for the carrier board. Could this supply (that is happening in the same net as the SoM PS_1V8 output that my custom carrier is trying to draw from) also be messing up with the board power net or the SoM power sequencing?

[jmats]

UPDATE:

I have since gotten my custom carrier board to successfully boot up and flash the TE0813, with no changes to the hardware/PCB. So it seems that my power sequencing setup works.

Still not 100% sure on the original cause of the issue (and it would be great to still have Trenz give their opinion on the Vivado error).

The main change I made was fix the board description in Vivado. Was initially using the TE0813 + TEBF0818 board file from the starter kit project, and changed that to just the TE0813 as in the test board project. Now I just have issues with getting any output from the UART-over-JTAG (but that, hopefully, is an unrelated issue...)

[Guillaume]

Hello Jmats,

I am also in the same situation, currently working on the schematics of a carrier board.

Thank you very much for sharing your work, it seems that I also understood the same things as you did.
I have to take time to read more in detail your questions, in the meantime I would eventually have some questions :

- How about the turn off ? how did you implement that ? is it "naturally" done or do you also have some sort of logic ?
- If I understand correctly, you directly connected the "PG signals" to the "EN signals" ? Because I was thinking about using the TPS22810DBVT as "enable" IC using those PG signals but your solution is actually easier.

Thank you in advance

[jmats]

Hi Guillaume,

About your questions:

- Currently I don't have an elegant turn-off solution implemented. I just cut the power supply to the carrier board.

- Precisely, the PG is routed directly to the respective EN, so that as soon as the PG signal comes high, it enables the following step.

As for the "enable IC" idea with the load-switch you mentioned: my understanding is that the PG signals are coming regulated from within the SoM, so indeed I don't think you would need it in these cases where you are just driving the enable signal.
But note that at the start of my power sequencing, the first enables use Pull-ups from the carrier board 3V3. For my application I can get away with this (my carrier board will be connected to an external rack with a regulated power supply, so I should have a stable 3V3) but it would be better engineering practice to indeed use a load switch or something else if you aren't sure of the stability of your carrier board supply. For those first enables, I actually have a set of jumpers which let me choose between activating via 3V3 pull-up OR from the PG of a power supervisor IC that is on my carrier (does OV/UV supervision, and general PG for the carrier).