TE0720 JTAG boot

[EddyD]

Hi,

For FPGA developments on Zynq boards (Zedboard, ZC702) I use the following method.
(The bootmode on the board is set to JTAG boot mode using the jumper/dipswitch (MIO5-2 to GND).)
Then, using the Xilinx SDK (and JTAG cable), I do the following sequence:
- Repower board (slide switch)
- Download .bit (SDK button "Program FPGA")
- Download .elf (a bare metal application to configure/control the FPGA-code) (SDK Run/Debug)

This is a flexible, clean, consistent, reproducable and very fast procedure:
- flexible: allows all development commands/tools/flows supported in SDK, from startup
- flexible: also possible on a boards that have no other functioning boot method (yet)
- clean: Zynq PS hasn't executed any code before
- consistent: PS configuration is always that of downloaded .elf, conform to downloaded .bit (SDK export)
- reproducable: start from repower, no influence of history after warm resets
- very fast: the time is only limited by the transfer time of .bit and .elf file (no boot delays).

My question:
  Is this also possible using TE0720 modules ? If so, how ?

Thanks,
wkr
Eddy

Some relevant quotes from ug585-Zynq-7000-TRM
"All boot modes, except the JTAG boot mode, execute code within the CPUs to configure both the PS
and PL sections of the Zynq-7000 AP SoC device. JTAG boot mode has control flexibility for a
development environment, but can only be used in a non-secure operating mode."

For non-JTAG boot modes:
"Post power-on, the boot ROM configures the required sections of the PS to read
the images from the selected boot device. The boot ROM first reads the boot header and based on
the configuration parameters set in the header, performs the authentication of the image, loads the
FSBL image from Flash to OCM, and hands over the control to the FSBL"

[Oleksandr Kiyenko]

Hello,

JTAG boot mode is not supported by TE0720. Easiest way to work with JTAG, is create and run dummy FSBL which initialize and stop processor after boot.

Best regards
Oleksandr Kiyenko

[pmsoftware]

Hello Oleksandr,
 so is this page of trenz wiki https://wiki.trenz-electronic.de/display/TE0720/Booting+U-Boot+via+JTAG out-of-date or not related with TE0720 module?
 can you give additional information how to stop processor using FSBL?
 
Best regards and thank you for support
Paolo

[Oleksandr Kiyenko]

Hello Paolo,

This page describe how to work with TE0720 using JTAG. But it's not true JTAG mode, mean that initially processor boot in SD or QSPI mode and then stopped and controlled via JTAG.
To stop processor you can modify FSBL, for example run infinite cycle after ps7_init() (like in "Old Instructions" chapter), so after initialization processor go to infinite loop which give you time to run debugger via JTAG.

Best regards
Oleksandr

[Oleksandr Kiyenko]

Hello

 You can get prepared elf file with bootloader which go to JTAG wait loop regardless of boot settings  http://www.trenz-electronic.de/fileadmin/docs/Trenz_Electronic/TE0720-GigaZee/reference_designs/TE0720-01-Common/FSBL_JTAG.elf

Best regards
Oleksandr

[pmsoftware]

Hi Oleksandr,
 thank you for preparing a JTAG_FSBL.
I made, following your istruction, the FSBL and it gives the same results of yours, so I guess my problem is little different.
I am using TE0701 carrier board for Te0720 module. With this configuration XMD give me this error:

Xilinx Microprocessor Debugger (XMD) Engine
Xilinx EDK 14.5 Build EDK_P.58f
Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.

XMD%
XMD% connect arm hw

JTAG chain configuration
--------------------------------------------------
Device   ID Code        IR Length    Part Name
 1       4ba00477           4        Cortex-A9
 2       23727093           6        XC7Z020
ERROR:
        MemAP is not enabled, cannot access DAP (CSW=0xc0000021)


XMD%

Best Regards
Paolo

[Oleksandr Kiyenko]

Hi
I just check this FSBL. I did:
1) create boot.bin from reference project using this elf file
2) write file to SD card
3) reboot board (Using S1 button)
4) Run Xilinx SDK
5) Run "Launch Hardware server" from "Xilinx Tools"
6) Go to "XMD Console" tab
Xilinx Microprocessor Debugger (XMD) Engine
Xilinx EDK 14.5 Build EDK_P.58f
Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.

XMD%
XMD%
Accepted a new TCLSock connection from 127.0.0.1 on port 57389
connect arm hw
ERROR:
   Failed to connect to Xilinx hw_server. Check if the
   hw_server is running and correct TCP port is used.

XMD% connect arm hw

JTAG chain configuration
--------------------------------------------------
Device   ID Code        IR Length    Part Name
 1       4ba00477           4        Cortex-A9
 2       23727093           6        XC7Z020

--------------------------------------------------
Enabling extended memory access checks for Zynq.
Writes to reserved memory are not permitted and reads return 0.
To disable this feature, run "debugconfig -memory_access_check disable".

--------------------------------------------------

CortexA9 Processor Configuration
-------------------------------------
Version.............................0x00000003
User ID.............................0x00000000
No of PC Breakpoints................6
No of Addr/Data Watchpoints.........4

Connected to "arm" target. id = 64
Starting GDB server for "arm" target (id = 64) at TCP port no 1234
XMD%

I can send you my boot.bin file if needed.
Best regards
Oleksandr

[pmsoftware]

Hi,
 It is correct and it works also for me.
 I only must not execute XMD outside Xilinix SDK.
 Thank you for help.

Best Regards
Paolo

[Matthias]

I'm having the same issue: I'm trying to use Xilinx SDK to connect through USB-JTAG to the TE0720 (on the TE0701).
I'm using ISE 14.7 on a 64bit machine.

Impact finds the Zynq through the Digilent cable without problems.

But when I use XSDK, "connect arm hw" on the XMD console fails with:
ERROR:
   Failed to connect to Xilinx hw_server. Check if the
   hw_server is running and correct TCP port is used.

In "Xilinx Tools"->"Configure JTAG settings", I have set "Digilent USB cable".

When I start hw_server on the console, I get on "connect arm hw":
incorrect WinDriver version
map_error 0x20000021
unable to open device: device not opened

When I run XMD from command line, I get
XMD% connect arm hw
JTAG chain configuration
--------------------------------------------------
Device   ID Code        IR Length    Part Name
 1       4ba00477           4        Cortex-A9
 2       23727093           6        XC7Z020
ERROR:
        MemAP is not enabled, cannot access DAP (CSW=0xc0000021)

My suspicion is that PJTAG_R is set to "independent", but there is no description on how to
check or change this from independant to cascaded in the System Controller!

I wanted to try above mentioned FSBL_JTAG.elf, but could not download this file.


I really need a JTAG to debug U-Boot, but I don't have a separate ARM JTAG debugger
How can use the USB-JTAG for this or the Xilinx Platform cable?

Thanks!

Matthias

PS: On ISE 14.7, there is no "Xilinx Tools"->"Launch Hardware Server"

[Antti Lukats]

I'm having the same issue: I'm trying to use Xilinx SDK to connect through USB-JTAG to the TE0720 (on the TE0701).
I'm using ISE 14.7 on a 64bit machine.

Impact finds the Zynq through the Digilent cable without problems.

But when I use XSDK, "connect arm hw" on the XMD console fails with:
ERROR:
   Failed to connect to Xilinx hw_server. Check if the
   hw_server is running and correct TCP port is used.

In "Xilinx Tools"->"Configure JTAG settings", I have set "Digilent USB cable".

When I start hw_server on the console, I get on "connect arm hw":
incorrect WinDriver version
map_error 0x20000021
unable to open device: device not opened

When I run XMD from command line, I get
XMD% connect arm hw
JTAG chain configuration
--------------------------------------------------
Device   ID Code        IR Length    Part Name
 1       4ba00477           4        Cortex-A9
 2       23727093           6        XC7Z020
ERROR:
        MemAP is not enabled, cannot access DAP (CSW=0xc0000021)

My suspicion is that PJTAG_R is set to "independent", but there is no description on how to
check or change this from independant to cascaded in the System Controller!

I wanted to try above mentioned FSBL_JTAG.elf, but could not download this file.


I really need a JTAG to debug U-Boot, but I don't have a separate ARM JTAG debugger
How can use the USB-JTAG for this or the Xilinx Platform cable?

Thanks!

Matthias

PS: On ISE 14.7, there is no "Xilinx Tools"->"Launch Hardware Server"

First, if the tools report that they can not connect to hw_server, or that win-driver version is wrong, then this should be FIXED.
Those issues are in no way related to TE0720.

If you with any tools see 2 devices in JTAG then this means that the JTAG is set to CASCADED. This is currently set as fixed option on TE0720.

We have done experiments with independent JTAG chain also, but it is really much more complicated, as the in independent mode the FSBL must still be executed to mux the JTAG pins onto some MIO or EMIO.

Independent mode is required only for the case that you want to use DS-5 for ARM, and chipscope for PL. Then 2 JTAG chains are needed.

MemAP is not enabled, cannot access DAP (CSW=0xc0000021)
####

this real old bad and famous ISSUE with Zynq. The issue was smaller (or different) with Zynq ES silicon, and got worse with production because the bootROM in production silicon has more security features enabled and takes potentially longer time to "give up" and release the JTAG interface.

the MemAP issue is a function of:

1 Xilinx software version
2 Zynq silicon revision
3 Cable type (FTDI or Platfrom cable)
4 Bootmode setting
5 FSBL code
6 something else that Xilinx only knows

We have seen it many many times. Unfortunately I have no universal recipe for the issue, Xilinx SDK debug resets the ARM cores, those will then run wild executing bootROM, JTAG is during this process partially disabled. The time what bootROM takes to enable the JTAG may be over 20 seconds. Most likely the debugger gives up, and reports memAP error.

In any cases, it is possible to use JTAG debugging with Xilinx SDK debuggers on TE0720, there is no need to "change the system controller" or use independent chain mode.

FSBL_JTAG.elf was just a dummy FSBL that should make the bootROM to enable the JTAG as fast as possible (without recovery image search, etc. etc..)

We are in the process of creating proper Vivado Board Part Interface flow support files for TE0720 for Vivado 2014.2, I will also then recreate some useful FSBL images and add more info in the wiki documents.

https://wiki.trenz-electronic.de/display/TE0720/DCC+Console

I found the DCC console very nice option, if UART is not available, we have used it in custom uboot debugging in some projects. Really nice.

br
Antti Lukats

[Matthias]

Thanks for the quick reply.

First, if the tools report that they can not connect to hw_server, or that win-driver version is wrong, then this should be FIXED.
Those issues are in no way related to TE0720.

You're right - sorry! I just tried the same ("connect arm hw" on XMD console) on my ZC702 board, and it shows the same errors.

Running "Xilinx Tools->Program FPGA" and "Run As Application (GDB)" works though on the Xilinx ZC702,
but it does not work on the TE0720/TE0701 (XSDK says "MemAP is not enabled, cannot access DAP (CSW=0xc0000021)"),
this is why I suspected the Trenz board.

this real old bad and famous ISSUE with Zynq

I googled for the "MemAP not enabled" error, and the only result I found was on the Trenz forum.
But from your hint, I also found these two links from xilinx.com
http://forums.xilinx.com/t5/7-Series-FPGAs/XC7Z045-2FFG676E-INIT-B-stays-low-cannot-access-DAP/td-p/361661
http://www.xilinx.com/support/answers/56195.html

Unfortunately, they didn't help me to find a solution.

"As a result, marginal designs that booted in ES might no longer boot with Production silicon." (AR# 56195)
I'm not sure what a marginal design is - could that be related to the timing of the bootup sequence?

But anyhow, there's probably nothing I can do on my side I can try, or can I?

In any cases, it is possible to use JTAG debugging with Xilinx SDK debuggers on TE0720, there is no need to "change the system controller" or use independent chain mode.

Ok, that's good to know.

FSBL_JTAG.elf was just a dummy FSBL that should make the bootROM to enable the JTAG as fast as possible (without recovery image search, etc. etc..)

Did that actually help? If yes, maybe Xilinx changed something in the later FSBL versions, so it would be worth looking there for a fix.
(Maybe using an earlier ISE/Vivado version).

Thanks for the hint with the DCC console - I'll have a look. Though, as far as I understand, this goes through (ARM) JTAG?

At the moment, I cannot connect at all to the ARM core through JTAG because of the "cannot access DAP" issues.

If you have any hints or ideas to try (bootup sequence/modes, special FSBL code, ...), please let me know

Thanks!

Matthias

[Antti Lukats]

Matthias,

just a quick question, what version of tools are you using?
Have you tried some latest (2014.1 or 2014.2) Vivado SDK Debugger?

Antti

[Matthias]

That's it! The Vivado SDK debugger (2013.4) works and can access the ARM core through JTAG

Until now, I'm using Impact 14.7 64bit (which works) and Xilinx SDK 14.7 (which gives the MemAP DAP error).

So the solution for now is to use Vivado SDK if ARM debugging through JTAG is required.

Thanks,
Matthias

[Antti Lukats]

That's it! The Vivado SDK debugger (2013.4) works and can access the ARM core through JTAG

Until now, I'm using Impact 14.7 64bit (which works) and Xilinx SDK 14.7 (which gives the MemAP DAP error).

So the solution for now is to use Vivado SDK if ARM debugging through JTAG is required.

Thanks,
Matthias

Good - the startup-reset-init timings did get changed a lot in the last days of ISE, so while 14.7 may be usable, there are more cases where it may cause problems.

We have seen lots of issues. Mem-DAP, 0x21, etc..

And of course as Vivado flow is so much different, it takes big courage to change horses.

But, this is the future: for Xilinx development Vivado is a MUST, and it is better to change as early as possible, if project timeline allows.

We are still currently supporting 14.7 for some customer designs, but for any new designs it is Vivado.

br
Antti Lukats