I'm having the same issue: I'm trying to use Xilinx SDK to connect through USB-JTAG to the TE0720 (on the TE0701).
I'm using ISE 14.7 on a 64bit machine.
Impact finds the Zynq through the Digilent cable without problems.
But when I use XSDK, "connect arm hw" on the XMD console fails with:
ERROR:
Failed to connect to Xilinx hw_server. Check if the
hw_server is running and correct TCP port is used.
In "Xilinx Tools"->"Configure JTAG settings", I have set "Digilent USB cable".
When I start hw_server on the console, I get on "connect arm hw":
incorrect WinDriver version
map_error 0x20000021
unable to open device: device not opened
When I run XMD from command line, I get
XMD% connect arm hw
JTAG chain configuration
--------------------------------------------------
Device ID Code IR Length Part Name
1 4ba00477 4 Cortex-A9
2 23727093 6 XC7Z020
ERROR:
MemAP is not enabled, cannot access DAP (CSW=0xc0000021)
My suspicion is that PJTAG_R is set to "independent", but there is no description on how to
check or change this from independant to cascaded in the System Controller!
I wanted to try above mentioned FSBL_JTAG.elf, but could not download this file.
I really need a JTAG to debug U-Boot, but I don't have a separate ARM JTAG debugger
How can use the USB-JTAG for this or the Xilinx Platform cable?
Thanks!
Matthias
PS: On ISE 14.7, there is no "Xilinx Tools"->"Launch Hardware Server"
First, if the tools report that they can not connect to hw_server, or that win-driver version is wrong, then this should be FIXED.
Those issues are in no way related to TE0720.
If you with any tools see 2 devices in JTAG then this means that the JTAG is set to CASCADED. This is currently set as fixed option on TE0720.
We have done experiments with independent JTAG chain also, but it is really much more complicated, as the in independent mode the FSBL must still be executed to mux the JTAG pins onto some MIO or EMIO.
Independent mode is required only for the case that you want to use DS-5 for ARM, and chipscope for PL. Then 2 JTAG chains are needed.
MemAP is not enabled, cannot access DAP (CSW=0xc0000021)
####
this real old bad and famous ISSUE with Zynq. The issue was smaller (or different) with Zynq ES silicon, and got worse with production because the bootROM in production silicon has more security features enabled and takes potentially longer time to "give up" and release the JTAG interface.
the MemAP issue is a function of:
1 Xilinx software version
2 Zynq silicon revision
3 Cable type (FTDI or Platfrom cable)
4 Bootmode setting
5 FSBL code
6 something else that Xilinx only knows
We have seen it many many times. Unfortunately I have no universal recipe for the issue, Xilinx SDK debug resets the ARM cores, those will then run wild executing bootROM, JTAG is during this process partially disabled. The time what bootROM takes to enable the JTAG may be over 20 seconds. Most likely the debugger gives up, and reports memAP error.
In any cases, it is possible to use JTAG debugging with Xilinx SDK debuggers on TE0720, there is no need to "change the system controller" or use independent chain mode.
FSBL_JTAG.elf was just a dummy FSBL that should make the bootROM to enable the JTAG as fast as possible (without recovery image search, etc. etc..)
We are in the process of creating proper Vivado Board Part Interface flow support files for TE0720 for Vivado 2014.2, I will also then recreate some useful FSBL images and add more info in the wiki documents.
https://wiki.trenz-electronic.de/display/TE0720/DCC+ConsoleI found the DCC console very nice option, if UART is not available, we have used it in custom uboot debugging in some projects. Really nice.
br
Antti Lukats