Controlling LED D1 & D2 on TEF1002

[axelbb@dtu.dk]

How do I control the D1 & D2 LEDs on the TEF1002 carrier board from the fpga? In my case TE0841-02-41I21-A. The diodes are controlled by the TEF1002 CPLD. The documentation (https://wiki.trenz-electronic.de/display/PD/TEF1002+SC+CPLD+MAX10) says:

  LED1 <= rgpio_out_data_i(19) when soc_rgpio_active='1' else Not(PCIE_PERST);
  LED2 <= rgpio_out_data_i(18) when soc_rgpio_active='1' else '0';

What is 'regpio_out_data_i'  and 'rgpio_active' ? Are these ports on CPLD rtl, or do they refer to some fpga rtl that can talk with the CPLD ?

[JH]

Hello,
yes it's an IP which can be used inside the FPGA which can be communicate between FPGA and CPLD with 3 wires:
https://wiki.trenz-electronic.de/display/PD/RGPIO
IP is available on the download area:
https://shop.trenz-electronic.de/en/Download/?path=Trenz_Electronic/Software/Vivado_IP_Core/2017.4

Used B2B pins (Table "Connection RGPIO to SoM"):
https://wiki.trenz-electronic.de/display/PD/TEF1002+SC+CPLD+MAX10#TEF1002SCCPLDMAX10-RGPIO

br
John