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How to create mcs file for Microblaze software

Started by genman4, September 14, 2013, 07:33:35 AM

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I am trying to implement a system that saves the FPGA configuration data to 2 FLAsh PROMs (xcf04s) connected in Master Serial Mode to the FPGA (Spartan 3E 1200).

What I have done so far

1. I have designed a simple test VHDL entity, verified its working.
2. I have configured the PROM with the bit stream by creating a .mcs file using Impact.
3. Turned OFF power, connected the Mode pins and turned the power ON.
Result: The FPGA was configured successfully.

1. The real system I am going to implement uses software. I implemented the system using the SDK and EDK for software.
2. How do I convert this software to a form that it can be stored in the PROM along with the hardware configuration, so that I can power up the FPGA and it will load these configuration

I have read the documentations XAPP501, XAPP138 and XAPP482 and the more I get confused.

What I am thinking is that I will convert a .elf file to .bit file and then use impact to convert it to .mcs file before configuring the PROM with it.

If I am correct above, does the .elf file contain all my project information (hardware and software) or just software.

Please let me know the best way to go about this.

Thank you

Oleksandr Kiyenko


To implement your project you need hardware and software parts:
1) Hardware part
- EDK core which will fetch data from Flash after FPGA programming. This core will generate CLK pilses to some FPGA pin (this pin should be connected to CCLK pin of FPGA) and read data from DIN pin. Also you need to control CE pin of Flash (usually it connected to FPGA Done pin, but in this case better to connect it to some other pin)
So resulted schematic will be
FPGA CCLK ---+-- Flash CLK
FPGA PinX-----|

FPGA PinY --- Flash CE

2) Software part
In software you need to implement First Stage Bootloader FSBL which will control core above and read Flash content
- Found signature in Flash (You can create your own system to pass information about beginning, start address and size of code or parse elf header)
- Read code from Flash and Write it to external memory
- Pass control to code in memory

After that you will need to write some software project which should be compiled to start from external memory (linkerscript configuration)
and create mcs file which will contain FPGA bitstream and this code
- Create bitstream (bit file) with hardware and FSBL in BRAM
- Create elf file whith you main code
- Create mcs file which will contain this 2 files (bitstream than elf)
- Write mcs to Flash

Best regards
Oleksandr Kiyenko


We would add some procedural references to the description above.
You can try (at least as a starting point) to use the srec bootloader template (aka First Stage Bootloader FSBL template) in SDK.

The SREC bootloader (aka First Stage Bootloader FSBL) could be created within SDK. If you export your hardware specification to SDK from XPS, a hardware platform should be automatically created in SDK. The "New C Project" dialog should then offer an SREC bootloader template.

You should set some parameters in the linker script.

For the .elf file, you could use the SDK "Program Flash" dialog (which can automatically convert the .elf to SREC).
The .bit file you write into the Flash needs to include the SREC bootloader created as described above.
You could get the bootloader into the .bit generated by ISE is SDK: Just use the "Program FPGA" dialog, specify your bootloader.elf as "ELF file to initialize to BRAM", and start "Program FPGA". As a by-product you get a "download.bit" in the Hardware Platform folder, which is the "marriage" of your system.bit with the bootloader.elf. This file can be written into the Flash using Impact.

The end address of the .bit file as specified by Impact is in 16-bit words, while SDK wants byte addresses in the "Program at offset" field of the "Program Flash" dialog. You have to double this number to avoid overwriting parts of the .bit with the SREC. 

Please find some references here:

1 - 3 - 4) Bit and elf to mcs

2) How to set or modify srec bootloader (aka First Stage Bootloader FSBL)

More references: