Author Topic: TE0320 FX2LP FIRMWARE ISSUE  (Read 3356 times)

oro06

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TE0320 FX2LP FIRMWARE ISSUE
« on: May 04, 2013, 05:44:35 PM »
Hi,

i'm currently using FX2LP to transfer data from fpga to host via EP6IN SLAVE FIFO BULK MODE
firmware is  te_usb_api.ver.3.2 from github
for reference from fw.c :
EP6CFG=0xE2        #enable, in, bulk, 512bytes, double buffered
EP6FIFOCFG=0x48 #signal line full 1 clk earlier, autoin, 8 bit wide

i succeeded for packets size <1024 and >1024 not multiples of 1024 up to several MB
but when data size is exactly 1024 the transfer hang.

during the write of the 1024th byte, fifofull flag is raised,
then datas are transfered to the usb host (i guess at the host driver buffer level but not seen by the client application)
and a new empty fifo is then presented to the fpga.
the problem is :
- PKTEND must be asserted to the last byte sent to indicate - en of batch an release last remaing datas
- PKTEND can't be asserted when flag full is raised, logic need to wait
- PKTEND can't be asserted when fifo is empty (as zero len packets are disabled in the firmware)
the only workaround i found was to write one more byte in this scenario and then asserting PKTEND

today i've tried to tweak the firmware
EP6FIFOCFG=0x48 #signal line full 1 clk earlier, autoin, 8 bit wide
by
EP6FIFOCFG=0x4C #signal line full 1 clk earlier, autoin, enable zero len packets, 8 bit wide

and now it runs perfectly whatever packet length have to be transfered

is there any reason to have ZLP not enabled in the firmware ?
could mainline firmware have this feature enabled ?

Thanks & regards
OR


Oleksandr Kiyenko

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Re: TE0320 FX2LP FIRMWARE ISSUE
« Reply #1 on: May 05, 2013, 12:47:10 PM »
Hello oro06,
Thanks for your feedback, you did great work!
There is no reasons to disable ZLP in this firmware. I'll update repository with your patch.