PHY reset Input

[GuinnessTrinker]

In latest Reference Designs you moved the external port PORT "ETHERNET_PHY_RST_N" from signal "ETHERNET_PHY_RST_N" (TEMAC-output) to "pll0_locked" (output of clock_generator_0 for DDR_MCB).

system.mhs:
# PORT ETHERNET_PHY_RST_N = ETHERNET_PHY_RST_N, DIR = O
 PORT ETHERNET_PHY_RST_N = pll0_locked, DIR = O


Why??

[Thorsten Trenz]

Hello,
It was made because PHY chip produce clock for the system. Unfortunatelly, in some rare cases, after power on PHY chip not produce clock till reset. So using PLL lock signal as reset to PHY garantee to have reset at begining of work and start of clock generation.
If you need to use ETHERNET_PHY_RST_N signal you can use it as AND with PLL lock.

Best Regards