Documentation inconsistencies of TE0720

[Gabriel]

Hello,

I'm designing a base board for a TE0720 module, taking inspiration from the TE0703 for some parts (Ethernet jack and FT2232). But I believe I have spotted a few mistakes in the documentation.

By far the most serious one is the power supply voltage range accepted for Bank 34: the schematics page 19 claims that it accepts an I/O voltage range of 1.2 to 3.3V, the TRM gives a slightly different range (1.25 to 3.3V).
Xilinx/AMD requires the VCCOs to be within 5% of their nominal value: which would be 1.26V max in that case.

This already reduces the range to a very tight 10mV (1.25 to 1.26V), something which is very difficult, if not impossible, to achieve.

In the schematics, there is a TPS3805H33 (which I used in one of my designs) voltage detector which detects the presence of the VCCIO34 supply on it sense pin. The documentation of said chip indicates that its negative-going threshold is 1.226V, with a typical (no min nor max given) hysteresis of 15mV, so the positive-going threshold is nominally 1.241V, but the documentation gives a dispersion of the threshold of ±18mV. So the worst case would be 1.259V, leaving a margin of only 1mV to allow the TE0720 to proceed with booting. At that point it becomes sensitive to external factors, like temperature (the thresholds have a tendency to rise at low temperatures).

Even when fulfilling the TRM requirements (1.25V), a shift of 9mV in the TPS3805H33 threshold (half the guaranteed dispersion) would prevent booting.

Finally, in the TPS3805H33 documentation, there is also a specification of the propagation delay versus overdrive voltage, the table value is meaningless (uses 5% overdrive/underdrive) for the case discussed here and figure 13 does not accurately show what happens at very low overdrive voltages, so I don't think it can be used here. It just still lowers my confidence in the possibility to use 1.2V IO standards for bank 34.

For these reasons, I seriously doubt that it is possible to design a TE0720 baseboard that reliably boots when VCCIO34 is 1.2V, even when tweaking the supply close to the maximum. It is playing with fire; I need a 1.2V bank in my design, and I have excluded bank 34.

The other documentation glitches/inconsistencies are much less serious:
- the schematics on page 19 claim that VCCIO13 is mandatory, but the TRM does not mention it and I believe it's not needed
- on the top right side of page 5, between the "PWR IN" and "PWR out" labels, there are 4 "CLK" labels for group3. Apparently they moved there by accident, and they should be associated with B35 L11 and L14 FPGA pins.