TE0818+TE0813

[hahmed]

Hi
I am currently using these boards with Vivado 2024.1.
I am trying to find a free running CLOCK where I can develop my design on PL logic.

The page 17 of SCH-TE0813-02-4AE81-A.pdf shows all clocks are going to MGT. These clocks are dedicated ones.

I tried to use A21 (clk_in_p) and A22(clk_in_n) to feed into IBUFDS

--IBUFDS_inst : IBUFDS
--port map (
--   O => CLK,   -- 1-bit output: Buffer output
--   I => clk_in_p,   -- 1-bit input: Diff_p buffer input (connect directly to top-level port)
--   IB => clk_in_n  -- 1-bit input: Diff_n buffer input (connect directly to top-level port)
--);


It does not like it.

Then, I commented out and try to debug a signal using

debug_0: ila_0
PORT MAP (
clk => clk_in_p,  -- only used A21 pin for clock
probe0(0) => DYNAMIC_BAUD_CLK,
probe1  => int_reg,
probe2(0) => RESET
);


It is not synthesizing and it is all because of clock.

Can you please find me a suitable free running clock and its associated pin for my PL FPGA?

Thank you