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Does Trenz have Master XDC files?

Started by dm1000, November 15, 2021, 06:20:10 PM

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dm1000

November 15, 2021, 06:20:10 PM
I have a TE0820 SOM and TE0701 carrier board.

Does Trenz provide a Master XDC file for this configuration?
Or a Git repo of Master XDC files for their boards?

Or a complete 'part0_pins.xml' file in the board definition files or BDF?  I have only found
empty 'part0_pins.xml' files.

JH

#1
November 16, 2021, 05:20:46 PM
Hi,
xdc depends on IO usage. We offer pinout excel sheet where you can get FPGA pin coordinates depending on carrier connector pin:
https://shop.trenz-electronic.de/de/Download/?path=Trenz_Electronic/Pinout
--> 4x5_series_pinout_tracelength.xlsx
IO Standard depends on your connection and IO usage.

We offer also schematics on the download area of the module and the carrier.
br
John

dm1000

#2
November 22, 2021, 10:56:55 PM
So, the user has to create their own XDC file?

I can see Trenz boards or board definition files in Vivado 2021.2.  But these BDF files look empty especially the pin file.

I get this message when I try to do a basic design

[Board 49-67] The board_part definition was not found for trenz.biz:te0820_2eg_1e:part0:2.0. This can happen sometimes when you use custom board part. You can resolve this issue by setting 'board.repoPaths' parameter, pointing to the location of custom board files. Valid board_part values can be retrieved with the 'get_board_parts' Tcl command.

I tried updating with the TCL command 'get_board_parts'.  I went to the path with Trenz boards for BDF files and the pin file is empty.

$ cat part0_pins.xml
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<!-- ##################################################################### -->
<!-- ##TE File Version:1.0-->
<!-- ##TE Last Modification:2017.08.27-->
<!-- ##################################################################### -->
<!-- ## replace part_name with correct FPGA PART from board.xml-->
<part_info part_name="xczu2eg-sfvc784-1-e">
  <pins>
    <!--insert ip pin settings and locations here, see ug895 or other board part files-->
  </pins>
</part_info>

Does Trenz have complete BDF files for a TE0701 with TE0820?

I am not finding either a more complete XDC file or BDF file to start some basic designs.

dm1000

#3
November 23, 2021, 01:28:05 AM
I have reviewed the BDF files in the GitHub repo "XilinxBoardStore".  I find complete pin assignments for Avnet, Digikey, TUL and Xilinx.
Trenz BDF files are the only ones that are not complete for the 'part0_pins.xml' files.  Why?   Digilent and Avnet dev boards - they provide complete
XDC files as well on other websites.  I have not found any complete XDC or BDF pin files for Trenz.   

JH

#4
November 23, 2021, 07:07:21 AM
Hi,
you need XDC for every different carrier and every different IO Standard which can be used theoretically with this module.

How should I know if you want to use IOs as differential IO or as single ended IO. ZynqMP supports different standards and this standards depends also on bank power which is variable on most of our modules.

PS: We have only newer board files  Xilinx Git Hub on Vivado 2020.2 branch. Update to 2021.2 branch an master branch is planned in next month.

br
John

dm1000

#5
November 23, 2021, 10:46:17 AM
Quote from: JH on November 23, 2021, 07:07:21 AM
Hi,
you need XDC for every different carrier and every different IO Standard which can be used theoretically with this module.

So, since Trenz provides a mind-numbing amount of different carrier and SOM board possible combinations - they do not provide any XDC or use-able BDF files?  I am still wondering why Xilinx, Avnet and Digikey decided to provide these files.  If the user modified the IO standard on the dev board - say by making a jumper change to a FPGA bank voltage - then the user can take the provided XDC or BDF file and modify it for the new IO standard.  Many other constraints will not need to be changed.  Things like the pin assignments do not change, for example.  I am very disappointed that it has taken many back and forth questions to confirm that Trenz does not provide any of these constraint files.  This means that I cannot create a quick/simple design in Vivado using the Trenz board files found in Vivado, without first having to write my own XDC file or update the empty BDF pin files.

How should I know if you want to use IOs as differential IO or as single ended IO. ZynqMP supports different standards and this standards depends also on bank power which is variable on most of our modules.

The user is not going to change the location constraints, drive strength or the IO standard for things like the DDR bus.  This is fixed by the HW design on the boards.  Same story for other dedicated board functions.  I do not believe that you are restricted to using only one master XDC file in Vivado.  Trenz could provide a XDC file for these type of dedicated board functions.

PS: We have only newer board files  Xilinx Git Hub on Vivado 2020.2 branch. Update to 2021.2 branch an master branch is planned in next month.

I don't understand your PS statement above. I should try to find the 2020.2 branch on which Git repo?

br board
John

JH

#6
November 23, 2021, 02:18:21 PM
Hi,
QuoteThe user is not going to change the location constraints, drive strength or the IO standard for things like the DDR bus.  This is fixed by the HW design on the boards.  Same story for other dedicated board functions.  I do not believe that you are restricted to using only one master XDC file in Vivado.  Trenz could provide a XDC file for these type of dedicated board functions.

DDR, USB, ETH, QSPI is connected on PS on TE0820. PS Setup has nothing todo with XDC, see ZynqMP TRM: https://www.xilinx.com/support/documentation/user_guides/ug1085-zynq-ultrascale-trm.pdf
So dedicated board functionality is included. XDC is for PL (FPGA) all FPGA IOs goes to B2B Connector and carrier decide the functionality

Basic PS setup is included in our board files and we offer also reference designs:
https://wiki.trenz-electronic.de/display/PD/TE0820+Reference+Designs

General Notes to our Board Files:  https://wiki.trenz-electronic.de/display/PD/Vivado+Board+Part+Flow


Quote
I don't understand your PS statement above. I should try to find the 2020.2 branch on which Git repo?
--> it's from your "I have reviewed the BDF files in the GitHub repo "XilinxBoardStore". "
Every Vivado Version use other branch: https://github.com/Xilinx/XilinxBoardStore
We also provide local version of the board files on our reference designs, see also:
https://wiki.trenz-electronic.de/display/PD/Vivado+Board+Part+Flow

br
John



dm1000

#7
November 23, 2021, 04:52:35 PM
My understanding is you can use either BDF or XDC files to constrain things like pins and IO. You should be able to constraint PS interfaces in an XDC file.

Keep in mind that I reviewed some of the BDF files found in the 'master' branch on the Git repo

https://github.com/Xilinx/XilinxBoardStore.git .

So, I checkout the '2020.2' branch in this Git repo and I look in the TE0820_2EG_1E folder (that is what SOM I have).  I still find empty 'part0_pins.xml' files for both the 1.0 and 2.0
folders. I do not see the value in these empty files. .

I have found other vendors like Avnet and Digilent to specify their pin assignments for their DDR,USB,ETH,QSPI interfaces in their 'part0_pins.xml' files. Before you
respond with yet more links - why not post an example XDC file provided by Trenz?  Or an example of a complete 'part0_pins.xml' file?

Here is an example of a Avnet 'part0_pins.xml' file I found in the same Git repo on the 2021.2 branch.  Why do they define the DDR interface and some GPIO?


<!--    ** **        **          **  ****      **  **********  ********** ®   
      **   **        **        **   ** **     **  **              **
     **     **        **      **    **  **    **  **              **
    **       **        **    **     **   **   **  *********       **
   **         **        **  **      **    **  **  **              **
  **           **        ****       **     ** **  **              **
**  .........  **        **        **      ****  **********      **
    ...........
                                    Reach Further™
Copyright (C) 2021, Avnet Inc - All rights reserved
Licensed under the Apache License, Version 2.0 (the "License"). You may
not use this file except in compliance with the License. A copy of the
License is located at
     http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
License for the specific language governing permissions and limitations
under the License.  -->
<part_info part_name="xczu7ev-fbvb900-1-i">
<pins>
<pin index="0" name="CPU_RESET" iostandard="LVCMOS18" loc="AA13"/>
<pin index="1" name="GPIO_DIP_SW0" iostandard="LVCMOS18" loc="AF13"/>
<pin index="2" name="GPIO_DIP_SW1" iostandard="LVCMOS18" loc="AG19"/>
<pin index="3" name="GPIO_DIP_SW2" iostandard="LVCMOS18" loc="AC13"/>
<pin index="4" name="GPIO_DIP_SW3" iostandard="LVCMOS18" loc="AC19"/>
<pin index="5" name="GPIO_DIP_SW4" iostandard="LVCMOS18" loc="AF1"/>
<pin index="6" name="GPIO_DIP_SW5" iostandard="LVCMOS18" loc="AH4"/>
<pin index="7" name="GPIO_DIP_SW6" iostandard="LVCMOS18" loc="AG9"/>
<pin index="8" name="GPIO_DIP_SW7" iostandard="LVCMOS18" loc="AE10"/>
<pin index="9" name="GPIO_LED_0_LS" iostandard="LVCMOS18" loc="AC14"/>
<pin index="10" name="GPIO_LED_1_LS" iostandard="LVCMOS18" loc="AD14"/>
<pin index="11" name="GPIO_LED_2_LS" iostandard="LVCMOS18" loc="AE14"/>
<pin index="12" name="GPIO_LED_3_LS" iostandard="LVCMOS18" loc="AE13"/>
<pin index="13" name="GPIO_LED_4_LS" iostandard="LVCMOS18" loc="AA14"/>
<pin index="14" name="GPIO_LED_5_LS" iostandard="LVCMOS18" loc="AB14"/>
<pin index="15" name="GPIO_LED_6_LS" iostandard="LVCMOS18" loc="AG4"/>
<pin index="16" name="GPIO_LED_7_LS" iostandard="LVCMOS18" loc="AG3"/>
<pin index="17" name="GPIO_PUSH_SW0" iostandard="LVCMOS18" loc="AB13"/>
<pin index="18" name="GPIO_PUSH_SW1" iostandard="LVCMOS18" loc="AA15"/>
<pin index="19" name="GPIO_PUSH_SW2" iostandard="LVCMOS18" loc="AB15"/>
<pin index="20" name="user_sysclk_p" iostandard="DIFF_SSTL12" loc="AC8"/>
<pin index="21" name="user_sysclk_n" iostandard="DIFF_SSTL12" loc="AC7"/>
<pin index="22" name="c0_ddr4_act_n" iostandard="SSTL12_DCI" loc="AE2" output_impedance="RDRV_40_40" slew="FAST"/>
<pin index="23" name="c0_ddr4_adr0" iostandard="SSTL12_DCI" loc="AC9" output_impedance="RDRV_40_40" slew="FAST"/>
<pin index="24" name="c0_ddr4_adr1" iostandard="SSTL12_DCI" loc="AD9" output_impedance="RDRV_40_40" slew="FAST"/>
<pin index="25" name="c0_ddr4_adr2" iostandard="SSTL12_DCI" loc="AC6" output_impedance="RDRV_40_40" slew="FAST"/>
<pin index="26" name="c0_ddr4_adr3" iostandard="SSTL12_DCI" loc="AD6" output_impedance="RDRV_40_40" slew="FAST"/>
<pin index="27" name="c0_ddr4_adr4" iostandard="SSTL12_DCI" loc="W8" output_impedance="RDRV_40_40" slew="FAST"/>
<pin index="28" name="c0_ddr4_adr5" iostandard="SSTL12_DCI" loc="Y8" output_impedance="RDRV_40_40" slew="FAST"/>
<pin index="29" name="c0_ddr4_adr6" iostandard="SSTL12_DCI" loc="AA8" output_impedance="RDRV_40_40" slew="FAST"/>
<pin index="30" name="c0_ddr4_adr7" iostandard="SSTL12_DCI" loc="AB8" output_impedance="RDRV_40_40" slew="FAST"/>
<pin index="31" name="c0_ddr4_adr8" iostandard="SSTL12_DCI" loc="W9" output_impedance="RDRV_40_40" slew="FAST"/>
<pin index="32" name="c0_ddr4_adr9" iostandard="SSTL12_DCI" loc="AC12" output_impedance="RDRV_40_40" slew="FAST"/>
<pin index="33" name="c0_ddr4_adr10" iostandard="SSTL12_DCI" loc="AD12" output_impedance="RDRV_40_40" slew="FAST"/>
<pin index="34" name="c0_ddr4_adr11" iostandard="SSTL12_DCI" loc="AA12" output_impedance="RDRV_40_40" slew="FAST"/>
<pin index="35" name="c0_ddr4_adr12" iostandard="SSTL12_DCI" loc="AA11" output_impedance="RDRV_40_40" slew="FAST"/>
<pin index="36" name="c0_ddr4_adr13" iostandard="SSTL12_DCI" loc="AB11" output_impedance="RDRV_40_40" slew="FAST"/>
<pin index="37" name="c0_ddr4_adr14" iostandard="SSTL12_DCI" loc="AC11" output_impedance="RDRV_40_40" slew="FAST"/>
<pin index="38" name="c0_ddr4_adr15" iostandard="SSTL12_DCI" loc="AD11" output_impedance="RDRV_40_40" slew="FAST"/>
<pin index="39" name="c0_ddr4_adr16" iostandard="SSTL12_DCI" loc="AD10" output_impedance="RDRV_40_40" slew="FAST"/>
<pin index="40" name="c0_ddr4_ba0" iostandard="SSTL12_DCI" loc="AB9" output_impedance="RDRV_40_40" slew="FAST"/>
<pin index="41" name="c0_ddr4_ba1" iostandard="SSTL12_DCI" loc="AB10" output_impedance="RDRV_40_40" slew="FAST"/>
<pin index="42" name="c0_ddr4_bg" iostandard="SSTL12_DCI" loc="Y10" output_impedance="RDRV_40_40" slew="FAST"/>
<pin index="43" name="c0_ddr4_ck_c" iostandard="DIFF_SSTL12_DCI" loc="AA7" output_impedance="RDRV_40_40" slew="FAST"/>
<pin index="44" name="c0_ddr4_ck_t" iostandard="DIFF_SSTL12_DCI" loc="Y7" output_impedance="RDRV_40_40" slew="FAST"/>
<pin index="45" name="c0_ddr4_cke" iostandard="SSTL12_DCI" loc="AE7" output_impedance="RDRV_40_40" slew="FAST"/>
<pin index="46" name="c0_ddr4_cs_n" iostandard="SSTL12_DCI" loc="AA10" output_impedance="RDRV_40_40" slew="FAST"/>
<pin index="47" name="c0_ddr4_dm_dbi_n0" iostandard="POD12_DCI" loc="AD2" output_impedance="RDRV_40_40" slew="FAST" ibuf_low_pwr="FALSE" odt="RTT_40" equalization="EQ_LEVEL2" pre_emphasis="RDRV_240"/>
<pin index="48" name="c0_ddr4_dm_dbi_n1" iostandard="POD12_DCI" loc="AD7" output_impedance="RDRV_40_40" slew="FAST" ibuf_low_pwr="FALSE" odt="RTT_40" equalization="EQ_LEVEL2" pre_emphasis="RDRV_240"/>
<pin index="49" name="c0_ddr4_dq0" iostandard="POD12_DCI" loc="AD1" output_impedance="RDRV_40_40" slew="FAST" ibuf_low_pwr="FALSE" odt="RTT_40" equalization="EQ_LEVEL2" pre_emphasis="RDRV_240"/>
<pin index="50" name="c0_ddr4_dq1" iostandard="POD12_DCI" loc="AE1" output_impedance="RDRV_40_40" slew="FAST" ibuf_low_pwr="FALSE" odt="RTT_40" equalization="EQ_LEVEL2" pre_emphasis="RDRV_240"/>
<pin index="51" name="c0_ddr4_dq2" iostandard="POD12_DCI" loc="AC3" output_impedance="RDRV_40_40" slew="FAST" ibuf_low_pwr="FALSE" odt="RTT_40" equalization="EQ_LEVEL2" pre_emphasis="RDRV_240"/>
<pin index="52" name="c0_ddr4_dq3" iostandard="POD12_DCI" loc="AC2" output_impedance="RDRV_40_40" slew="FAST" ibuf_low_pwr="FALSE" odt="RTT_40" equalization="EQ_LEVEL2" pre_emphasis="RDRV_240"/>
<pin index="53" name="c0_ddr4_dq4" iostandard="POD12_DCI" loc="AB1" output_impedance="RDRV_40_40" slew="FAST" ibuf_low_pwr="FALSE" odt="RTT_40" equalization="EQ_LEVEL2" pre_emphasis="RDRV_240"/>
<pin index="54" name="c0_ddr4_dq5" iostandard="POD12_DCI" loc="AC1" output_impedance="RDRV_40_40" slew="FAST" ibuf_low_pwr="FALSE" odt="RTT_40" equalization="EQ_LEVEL2" pre_emphasis="RDRV_240"/>
<pin index="55" name="c0_ddr4_dq6" iostandard="POD12_DCI" loc="AA2" output_impedance="RDRV_40_40" slew="FAST" ibuf_low_pwr="FALSE" odt="RTT_40" equalization="EQ_LEVEL2" pre_emphasis="RDRV_240"/>
<pin index="56" name="c0_ddr4_dq7" iostandard="POD12_DCI" loc="AA1" output_impedance="RDRV_40_40" slew="FAST" ibuf_low_pwr="FALSE" odt="RTT_40" equalization="EQ_LEVEL2" pre_emphasis="RDRV_240"/>
<pin index="57" name="c0_ddr4_dq8" iostandard="POD12_DCI" loc="AB6" output_impedance="RDRV_40_40" slew="FAST" ibuf_low_pwr="FALSE" odt="RTT_40" equalization="EQ_LEVEL2" pre_emphasis="RDRV_240"/>
<pin index="58" name="c0_ddr4_dq9" iostandard="POD12_DCI" loc="AB5" output_impedance="RDRV_40_40" slew="FAST" ibuf_low_pwr="FALSE" odt="RTT_40" equalization="EQ_LEVEL2" pre_emphasis="RDRV_240"/>
<pin index="59" name="c0_ddr4_dq10" iostandard="POD12_DCI" loc="AD5" output_impedance="RDRV_40_40" slew="FAST" ibuf_low_pwr="FALSE" odt="RTT_40" equalization="EQ_LEVEL2" pre_emphasis="RDRV_240"/>
<pin index="60" name="c0_ddr4_dq11" iostandard="POD12_DCI" loc="AE5" output_impedance="RDRV_40_40" slew="FAST" ibuf_low_pwr="FALSE" odt="RTT_40" equalization="EQ_LEVEL2" pre_emphasis="RDRV_240"/>
<pin index="61" name="c0_ddr4_dq12" iostandard="POD12_DCI" loc="AB4" output_impedance="RDRV_40_40" slew="FAST" ibuf_low_pwr="FALSE" odt="RTT_40" equalization="EQ_LEVEL2" pre_emphasis="RDRV_240"/>
<pin index="62" name="c0_ddr4_dq13" iostandard="POD12_DCI" loc="AC4" output_impedance="RDRV_40_40" slew="FAST" ibuf_low_pwr="FALSE" odt="RTT_40" equalization="EQ_LEVEL2" pre_emphasis="RDRV_240"/>
<pin index="63" name="c0_ddr4_dq14" iostandard="POD12_DCI" loc="AA6" output_impedance="RDRV_40_40" slew="FAST" ibuf_low_pwr="FALSE" odt="RTT_40" equalization="EQ_LEVEL2" pre_emphasis="RDRV_240"/>
<pin index="64" name="c0_ddr4_dq15" iostandard="POD12_DCI" loc="AA5" output_impedance="RDRV_40_40" slew="FAST" ibuf_low_pwr="FALSE" odt="RTT_40" equalization="EQ_LEVEL2" pre_emphasis="RDRV_240"/>
<pin index="65" name="c0_ddr4_dqs_c0" iostandard="DIFF_POD12_DCI" loc="AB3" output_impedance="RDRV_40_40" slew="FAST" ibuf_low_pwr="FALSE" odt="RTT_40" equalization="EQ_LEVEL2" pre_emphasis="RDRV_240"/>
<pin index="66" name="c0_ddr4_dqs_c1" iostandard="DIFF_POD12_DCI" loc="AE4" output_impedance="RDRV_40_40" slew="FAST" ibuf_low_pwr="FALSE" odt="RTT_40" equalization="EQ_LEVEL2" pre_emphasis="RDRV_240"/>
<pin index="67" name="c0_ddr4_dqs_t1" iostandard="DIFF_POD12_DCI" loc="AD4" output_impedance="RDRV_40_40" slew="FAST" ibuf_low_pwr="FALSE" odt="RTT_40" equalization="EQ_LEVEL2" pre_emphasis="RDRV_240"/>
<pin index="68" name="c0_ddr4_dqs_t0" iostandard="DIFF_POD12_DCI" loc="AA3" output_impedance="RDRV_40_40" slew="FAST" ibuf_low_pwr="FALSE" odt="RTT_40" equalization="EQ_LEVEL2" pre_emphasis="RDRV_240"/>
<pin index="69" name="c0_ddr4_odt" iostandard="SSTL12_DCI" loc="AE3" output_impedance="RDRV_40_40" slew="FAST"/>
<pin index="70" name="c0_ddr4_reset_n" iostandard="LVCMOS12" loc="Y1" drive="8"/>
</pins>
</part_info>

I found this file in the Git repo here

/Avnet/ultrazed_7ev_cc/1.5 (2020.2) $ ls -l
total 360
-rw-rw-r-- 1 dave dave  17113 Nov 23 08:14 board.xml
-rw-rw-r-- 1 dave dave     95 Nov 23 08:14 changelog.txt
-rw-rw-r-- 1 dave dave    718 Nov 23 08:14 LICENSE
-rw-rw-r-- 1 dave dave  10466 Nov 23 08:14 part0_pins.xml
-rw-rw-r-- 1 dave dave  25724 Nov 23 08:14 preset.xml
-rw-rw-r-- 1 dave dave 294402 Nov 23 08:14 ultrazed_ev_carrier_card.jpg
-rw-rw-r-- 1 dave dave    816 Nov 23 08:14 xitem.json
/Avnet/ultrazed_7ev_cc/1.5 (2020.2) $

If this board can be configured for a different IO bank voltage - say for GPIO - it would not be a major effort to change the 'iostandard' in this 'part0_pins.xml' file.

JH

#8
November 23, 2021, 05:03:08 PM Last Edit: November 23, 2021, 05:05:07 PM by JH
Hi,

UltraZed has DDR on PS and on PL:
https://www.avnet.com/wps/portal/us/products/avnet-boards/avnet-board-families/ultrazed/ultrazed-ev/ultrazed-ev-board-family


for example:
"<pin index="24" name="c0_ddr4_adr1" iostandard="SSTL12_DCI" loc="AD9" output_impedance="RDRV_40_40" slew="FAST"/>"
of xczu7ev-fbvb900-1-i is PL(Programmable Logic, where you need xdc) IO see:
https://www.xilinx.com/support/packagefiles/zuppackages/xczu7evfbvb900pkg.txt
--> AD9   IO_L7N_T1L_N1_QBC_AD13N_66          1L                 66    HP        NA                 


br
John   

dm1000

#9
November 23, 2021, 07:06:43 PM
It looks to me that this UltraZed board from Avnet has constraints in two places.

First, they have DDR and some GPIO in the BDF file 'part0_pins.xml'
And they also provide a Master User Constraint List in XDC format below.  DDR is not defined here.
But the user would have to comment-out what is not used in the design. 

Here is a section of that file.

set_property IOSTANDARD LVCMOS33 [get_ports {PLPMOD2_D0}]
set_property IOSTANDARD LVCMOS33 [get_ports {PLPMOD2_D1}]
set_property IOSTANDARD LVCMOS33 [get_ports {PLPMOD2_D2}]
set_property IOSTANDARD LVCMOS33 [get_ports {PLPMOD2_D3}]
set_property IOSTANDARD LVCMOS33 [get_ports {PLPMOD2_D4}]
set_property IOSTANDARD LVCMOS33 [get_ports {PLPMOD2_D5}]
set_property IOSTANDARD LVCMOS33 [get_ports {PLPMOD2_D6}]
set_property IOSTANDARD LVCMOS33 [get_ports {PLPMOD2_D7}]


# PL HDMI Interface
#
set_property PACKAGE_PIN D5  [get_ports {U9_IN_D0N}];      # GTH0_TX_N
set_property PACKAGE_PIN D6  [get_ports {U9_IN_D0P}];      # GTH0_TX_P
set_property PACKAGE_PIN C7  [get_ports {U9_IN_D1N}];      # GTH1_TX_N
set_property PACKAGE_PIN C8  [get_ports {U9_IN_D1P}];      # GTH1_TX_P
set_property PACKAGE_PIN B5  [get_ports {U9_IN_D2N}];      # GTH2_TX_N
set_property PACKAGE_PIN B6  [get_ports {U9_IN_D2P}];      # GTH2_TX_P

set_property PACKAGE_PIN AE15 [get_ports {U9_IN_CLKN}];   # HP_DP_23_N
set_property PACKAGE_PIN AD15 [get_ports {U9_IN_CLKP}];   # HP_DP_23_P
set_property PACKAGE_PIN A14  [get_ports {U9_OE}];      # HD_SE_13_P
set_property PACKAGE_PIN E13  [get_ports {U9_SCL_SRC}];   # HD_SE_17_GC_N
set_property PACKAGE_PIN E14  [get_ports {U9_SDA_SRC}];   # HD_SE_17_GC_P
set_property PACKAGE_PIN F13  [get_ports {U9_SCL_CTL}];   # HD_SE_18_GC_N
set_property PACKAGE_PIN G13  [get_ports {U9_SDA_CTL}];   # HD_SE_18_GC_P
set_property PACKAGE_PIN A13  [get_ports {U8_CEC_A}];      # HD_SE_13_N
set_property PACKAGE_PIN C14  [get_ports {U8_HPD_A}];      # HD_SE_14_P


set_property PACKAGE_PIN D1  [get_ports {J12_D0N}];         # GTH0_RX_N
set_property PACKAGE_PIN D2  [get_ports {J12_D0P}];         # GTH0_RX_P
set_property PACKAGE_PIN C3  [get_ports {J12_D1N}];         # GTH1_RX_N
set_property PACKAGE_PIN C4  [get_ports {J12_D1P}];         # GTH1_RX_P
set_property PACKAGE_PIN B1  [get_ports {J12_D2N}];         # GTH2_RX_N
set_property PACKAGE_PIN B2  [get_ports {J12_D2P}];         # GTH2_RX_P
set_property PACKAGE_PIN B9  [get_ports {J12_CLKN}];         # GTH_REFCLK1_N
set_property PACKAGE_PIN B10 [get_ports {J12_CLKP}];         # GTH_REFCLK1_P

set_property PACKAGE_PIN G14  [get_ports {HDMI_RX_PWR_DET}];   # HD_SE_15_N
set_property PACKAGE_PIN H14  [get_ports {HDMI_RX_HPD}];      # HD_SE_15_P
set_property PACKAGE_PIN B14  [get_ports {U11_CEC_A}];      # HD_SE_14_N
set_property PACKAGE_PIN E12  [get_ports {U11_SCL_A}];      # HD_SE_19_GC_N
set_property PACKAGE_PIN F12  [get_ports {U11_SDA_A}];      # HD_SE_19_GC_P


# PL 3G-SDI Interface
#
set_property PACKAGE_PIN A7  [get_ports {U13_SDIN}];      # GTH3_TX_N
set_property PACKAGE_PIN A8  [get_ports {U13_SDIP}];      # GTH3_TX_P
set_property PACKAGE_PIN A3  [get_ports {U12_SDON}];      # GTH3_RX_N
set_property PACKAGE_PIN A4  [get_ports {U12_SDOP}];      # GTH3_RX_P


# PL SFP+ Interface
#
set_property PACKAGE_PIN H5  [get_ports {SFP1_TD_N}];      # GTH4_TX_N
set_property PACKAGE_PIN H6  [get_ports {SFP1_TD_P}];      # GTH4_TX_P
set_property PACKAGE_PIN H1  [get_ports {SFP1_RD_N}];      # GTH4_RX_N
set_property PACKAGE_PIN H2  [get_ports {SFP1_RD_P}];      # GTH4_RX_P
set_property PACKAGE_PIN J15 [get_ports {SFP1_TX_DIS}];   # HD_SE_09_P
set_property PACKAGE_PIN J14 [get_ports {LOS1}];      # HD_SE_09_N
set_property PACKAGE_PIN C17 [get_ports {SFP1_SDA}];      # HD_SE_10_P
set_property PACKAGE_PIN B16 [get_ports {SFP1_SCL}];      # HD_SE_10_N

set_property PACKAGE_PIN G7  [get_ports {SFP2_TD_N}];      # GTH5_TX_N
set_property PACKAGE_PIN G8  [get_ports {SFP2_TD_P}];      # GTH5_TX_P
set_property PACKAGE_PIN G3  [get_ports {SFP2_RD_N}];      # GTH5_RX_N
set_property PACKAGE_PIN G4  [get_ports {SFP2_RD_P}];      # GTH5_RX_P
set_property PACKAGE_PIN L15 [get_ports {SFP2_TX_DIS}];   # HD_SE_11_P
set_property PACKAGE_PIN L14 [get_ports {LOS2}];      # HD_SE_11_N
set_property PACKAGE_PIN B12 [get_ports {SFP2_SDA}];      # HD_SE_12_P
set_property PACKAGE_PIN A12 [get_ports {SFP2_SCL}];      # HD_SE_12_N


# GTH Differential Clocks From the IDT 8T49N241 Device
#
set_property PACKAGE_PIN D9  [get_ports {GTH_REFCLK0_N}]
set_property PACKAGE_PIN D10 [get_ports {GTH_REFCLK0_P}]
set_property PACKAGE_PIN H9  [get_ports {GTH_REFCLK2_N}]
set_property PACKAGE_PIN H10 [get_ports {GTH_REFCLK2_P}]
set_property PACKAGE_PIN J7  [get_ports {GTH_REFCLK5_N}]
set_property PACKAGE_PIN J8  [get_ports {GTH_REFCLK5_P}]


# GTH SMA Clocks
#
set_property PACKAGE_PIN F9  [get_ports {GTH_REFCLK3_N}]
set_property PACKAGE_PIN F10  [get_ports {GTH_REFCLK3_P}]
set_property PACKAGE_PIN N7  [get_ports {GTH_REFCLK7_N}]
set_property PACKAGE_PIN N8  [get_ports {GTH_REFCLK7_P}]


# PL LVDS Touch Panel Interface
#
set_property PACKAGE_PIN AH12 [get_ports {TP_D0_P}];      # HP_DP_42_P
set_property PACKAGE_PIN AJ12 [get_ports {TP_D0_N}];      # HP_DP_42_N
set_property PACKAGE_PIN AE9 [get_ports {TP_D1_P}];      # HP_DP_43_P
set_property PACKAGE_PIN AE8 [get_ports {TP_D1_N}];      # HP_DP_43_N
set_property PACKAGE_PIN AH3 [get_ports {TP_D2_P}];      # HP_DP_44_P
set_property PACKAGE_PIN AH2 [get_ports {TP_D2_N}];      # HP_DP_44_N
set_property PACKAGE_PIN AK3 [get_ports {TP_D3_P}];      # HP_DP_45_P
set_property PACKAGE_PIN AK2 [get_ports {TP_D3_N}];      # HP_DP_45_N
set_property PACKAGE_PIN AG1 [get_ports {TP_CLK_P}];      # HP_DP_46_P
set_property PACKAGE_PIN AH1 [get_ports {TP_CLK_N}];      # HP_DP_46_N
set_property PACKAGE_PIN H13  [get_ports {TP_SCL}];      # HD_SE_21_P
set_property PACKAGE_PIN H12  [get_ports {TP_SDA}];      # HD_SE_21_N
set_property PACKAGE_PIN C12  [get_ports {TP_IRQ_N}];      # HD_SE_20_N

set_property IOSTANDARD LVDS [get_ports {TP_CLK_P}]
set_property IOSTANDARD LVDS [get_ports {TP_CLK_N}]
set_property IOSTANDARD LVDS [get_ports {TP_D0_P}]
set_property IOSTANDARD LVDS [get_ports {TP_D0_N}]
set_property IOSTANDARD LVDS [get_ports {TP_D1_P}]
set_property IOSTANDARD LVDS [get_ports {TP_D1_N}]
set_property IOSTANDARD LVDS [get_ports {TP_D2_P}]
set_property IOSTANDARD LVDS [get_ports {TP_D2_N}]
set_property IOSTANDARD LVDS [get_ports {TP_D3_P}]
set_property IOSTANDARD LVDS [get_ports {TP_D3_N}]
set_property IOSTANDARD LVCMOS33 [get_ports {TP_INT#}]
set_property IOSTANDARD LVCMOS33 [get_ports {TP_SCL}]
set_property IOSTANDARD LVCMOS33 [get_ports {TP_SDA}]


# FMC HPC Interface
#
set_property PACKAGE_PIN AH14 [get_ports {FMC_CLK0_M2C_N}];     # HP_DP_14_GC_N
set_property PACKAGE_PIN AG14 [get_ports {FMC_CLK0_M2C_P}];     # HP_DP_14_GC_P
set_property PACKAGE_PIN AJ7 [get_ports {FMC_CLK1_M2C_N}];     # HP_DP_34_GC_N
set_property PACKAGE_PIN AH7 [get_ports {FMC_CLK1_M2C_P}];     # HP_DP_34_GC_P
set_property PACKAGE_PIN AF17 [get_ports {FMC_LA00_CC_N}];      # HP_DP_12_GC_N
set_property PACKAGE_PIN AF16 [get_ports {FMC_LA00_CC_P}];     # HP_DP_12_GC_P
set_property PACKAGE_PIN AE17 [get_ports {FMC_LA01_CC_N}];     # HP_DP_13_GC_N
set_property PACKAGE_PIN AD17 [get_ports {FMC_LA01_CC_P}];     # HP_DP_13_GC_P

set_property PACKAGE_PIN AH18 [get_ports {FMC_LA02_N}];        # HP_DP_00_N
set_property PACKAGE_PIN AG18 [get_ports {FMC_LA02_P}];        # HP_DP_00_P
set_property PACKAGE_PIN AF18 [get_ports {FMC_LA03_N}];        # HP_DP_01_N
set_property PACKAGE_PIN AE18 [get_ports {FMC_LA03_P}];        # HP_DP_01_P
set_property PACKAGE_PIN AJ17 [get_ports {FMC_LA04_N}];        # HP_DP_02_N
set_property PACKAGE_PIN AH17 [get_ports {FMC_LA04_P}];        # HP_DP_02_P
set_property PACKAGE_PIN AE19 [get_ports {FMC_LA05_N}];        # HP_DP_03_N
set_property PACKAGE_PIN AD19 [get_ports {FMC_LA05_P}];        # HP_DP_03_P
set_property PACKAGE_PIN AC18 [get_ports {FMC_LA06_N}];        # HP_DP_04_N
set_property PACKAGE_PIN AC17 [get_ports {FMC_LA06_P}];        # HP_DP_04_P
set_property PACKAGE_PIN AB16 [get_ports {FMC_LA07_N}];        # HP_DP_05_N
set_property PACKAGE_PIN AA16 [get_ports {FMC_LA07_P}];        # HP_DP_05_P
set_property PACKAGE_PIN AK16 [get_ports {FMC_LA08_N}];        # HP_DP_06_N
set_property PACKAGE_PIN AJ16 [get_ports {FMC_LA08_P}];        # HP_DP_06_P
set_property PACKAGE_PIN AK18 [get_ports {FMC_LA09_N}];       # HP_DP_07_N
set_property PACKAGE_PIN AK17 [get_ports {FMC_LA09_P}];        # HP_DP_07_P
set_property PACKAGE_PIN AH16 [get_ports {FMC_LA10_N}];        # HP_DP_08_N
set_property PACKAGE_PIN AG16 [get_ports {FMC_LA10_P}];        # HP_DP_08_P
set_property PACKAGE_PIN AD16 [get_ports {FMC_LA11_N}];        # HP_DP_09_N
set_property PACKAGE_PIN AC16 [get_ports {FMC_LA11_P}];        # HP_DP_09_P
set_property PACKAGE_PIN AK14 [get_ports {FMC_LA12_N}];        # HP_DP_10_N
set_property PACKAGE_PIN AJ14 [get_ports {FMC_LA12_P}];        # HP_DP_10_P
set_property PACKAGE_PIN AK15 [get_ports {FMC_LA13_N}];        # HP_DP_11_N
set_property PACKAGE_PIN AJ15 [get_ports {FMC_LA13_P}];        # HP_DP_11_P
set_property PACKAGE_PIN AG15 [get_ports {FMC_LA14_N}];        # HP_DP_15_GC_N
set_property PACKAGE_PIN AF15 [get_ports {FMC_LA14_P}];        # HP_DP_15_GC_P
set_property PACKAGE_PIN AK12 [get_ports {FMC_LA15_N}];        # HP_DP_16_N
set_property PACKAGE_PIN AK13 [get_ports {FMC_LA15_P}];        # HP_DP_16_P
set_property PACKAGE_PIN AH13 [get_ports {FMC_LA16_N}];        # HP_DP_17_N
set_property PACKAGE_PIN AG13 [get_ports {FMC_LA16_P}];        # HP_DP_17_P
set_property PACKAGE_PIN AG5 [get_ports {FMC_LA17_CC_N}];     # HP_DP_32_GC_N
set_property PACKAGE_PIN AG6 [get_ports {FMC_LA17_CC_P}];     # HP_DP_32_GC_P
set_property PACKAGE_PIN AJ6 [get_ports {FMC_LA18_CC_N}];     # HP_DP_33_GC_N
set_property PACKAGE_PIN AH6 [get_ports {FMC_LA18_CC_P}];     # HP_DP_33_GC_P
set_property PACKAGE_PIN AG10 [get_ports {FMC_LA19_N}];        # HP_DP_24_N
set_property PACKAGE_PIN AF10 [get_ports {FMC_LA19_P}];        # HP_DP_24_P
set_property PACKAGE_PIN AK10 [get_ports {FMC_LA20_N}];        # HP_DP_25_N
set_property PACKAGE_PIN AJ10 [get_ports {FMC_LA20_P}];        # HP_DP_25_P
set_property PACKAGE_PIN AF7 [get_ports {FMC_LA21_N}];        # HP_DP_26_N
set_property PACKAGE_PIN AF8 [get_ports {FMC_LA21_P}];        # HP_DP_26_P
set_property PACKAGE_PIN AF11 [get_ports {FMC_LA22_N}];        # HP_DP_27_N
set_property PACKAGE_PIN AF12 [get_ports {FMC_LA22_P}];        # HP_DP_27_P
set_property PACKAGE_PIN AK5 [get_ports {FMC_LA23_N}];        # HP_DP_28_N
set_property PACKAGE_PIN AJ5 [get_ports {FMC_LA23_P}];        # HP_DP_28_P
set_property PACKAGE_PIN AK6 [get_ports {FMC_LA24_N}];        # HP_DP_29_N
set_property PACKAGE_PIN AK7 [get_ports {FMC_LA24_P}];        # HP_DP_29_P
set_property PACKAGE_PIN AF5 [get_ports {FMC_LA25_N}];        # HP_DP_30_N
set_property PACKAGE_PIN AF6 [get_ports {FMC_LA25_P}];        # HP_DP_30_P
set_property PACKAGE_PIN AK8 [get_ports {FMC_LA26_N}];        # HP_DP_31_N
set_property PACKAGE_PIN AK9 [get_ports {FMC_LA26_P}];        # HP_DP_31_P
set_property PACKAGE_PIN AH8 [get_ports {FMC_LA27_N}];        # HP_DP_35_GC_N
set_property PACKAGE_PIN AG8 [get_ports {FMC_LA27_P}];        # HP_DP_35_GC_P
set_property PACKAGE_PIN AK11 [get_ports {FMC_LA28_N}];        # HP_DP_36_N
set_property PACKAGE_PIN AJ11 [get_ports {FMC_LA28_P}];        # HP_DP_36_P
set_property PACKAGE_PIN AK4 [get_ports {FMC_LA29_N}];        # HP_DP_37_N
set_property PACKAGE_PIN AJ4 [get_ports {FMC_LA29_P}];        # HP_DP_37_P
set_property PACKAGE_PIN AJ1 [get_ports {FMC_LA30_N}];        # HP_DP_38_N
set_property PACKAGE_PIN AJ2 [get_ports {FMC_LA30_P}];        # HP_DP_38_P
set_property PACKAGE_PIN AF2 [get_ports {FMC_LA31_N}];       # HP_DP_39_N
set_property PACKAGE_PIN AF3 [get_ports {FMC_LA31_P}];        # HP_DP_39_P
set_property PACKAGE_PIN AJ9 [get_ports {FMC_LA32_N}];        # HP_DP_40_N
set_property PACKAGE_PIN AH9 [get_ports {FMC_LA32_P}];        # HP_DP_40_P
set_property PACKAGE_PIN AH11 [get_ports {FMC_LA33_N}];        # HP_DP_41_N
set_property PACKAGE_PIN AG11 [get_ports {FMC_LA33_P}];        # HP_DP_41_P
set_property PACKAGE_PIN J12  [get_ports {FMC_SCL}];        # HD_SE_22_N
set_property PACKAGE_PIN K13  [get_ports {FMC_SDA}];        # HD_SE_22_P
set_property PACKAGE_PIN K12   [get_ports {FMC_PRSNT_M2C#}];     # HD_SE_23_P
set_property PACKAGE_PIN K11  [get_ports {FMC_TRST#}];        # HD_SE_23_N

set_property IOSTANDARD LVDS [get_ports {FMC_CLK0_M2C_N}]
set_property IOSTANDARD LVDS [get_ports {FMC_CLK0_M2C_P}]
set_property IOSTANDARD LVDS [get_ports {FMC_CLK1_M2C_N}]
set_property IOSTANDARD LVDS [get_ports {FMC_CLK1_M2C_P}]
set_property IOSTANDARD LVCMOS18 [get_ports {FMC_LA00_CC_P}]
set_property IOSTANDARD LVCMOS18 [get_ports {FMC_LA00_CC_N}]
set_property IOSTANDARD LVCMOS18 [get_ports {FMC_LA01_CC_P}]
set_property IOSTANDARD LVCMOS18 [get_ports {FMC_LA01_CC_N}]
set_property IOSTANDARD LVCMOS18 [get_ports {FMC_LA02_P}]
set_property IOSTANDARD LVCMOS18 [get_ports {FMC_LA02_N}]
set_property IOSTANDARD LVCMOS18 [get_ports {FMC_LA03_P}]
set_property IOSTANDARD LVCMOS18 [get_ports {FMC_LA03_N}]
set_property IOSTANDARD LVCMOS18 [get_ports {FMC_LA04_P}]
set_property IOSTANDARD LVCMOS18 [get_ports {FMC_LA04_N}]
set_property IOSTANDARD LVCMOS18 [get_ports {FMC_LA05_P}]
set_property IOSTANDARD LVCMOS18 [get_ports {FMC_LA05_N}]
set_property IOSTANDARD LVCMOS18 [get_ports {FMC_LA06_P}]
set_property IOSTANDARD LVCMOS18 [get_ports {FMC_LA06_N}]
set_property IOSTANDARD LVCMOS18 [get_ports {FMC_LA07_P}]
set_property IOSTANDARD LVCMOS18 [get_ports {FMC_LA07_N}]
set_property IOSTANDARD LVCMOS18 [get_ports {FMC_LA08_P}]
set_property IOSTANDARD LVCMOS18 [get_ports {FMC_LA08_N}]
set_property IOSTANDARD LVCMOS18 [get_ports {FMC_LA09_P}]
set_property IOSTANDARD LVCMOS18 [get_ports {FMC_LA09_N}]
set_property IOSTANDARD LVCMOS18 [get_ports {FMC_LA10_P}]
set_property IOSTANDARD LVCMOS18 [get_ports {FMC_LA10_N}]
set_property IOSTANDARD LVCMOS18 [get_ports {FMC_LA11_P}]
set_property IOSTANDARD LVCMOS18 [get_ports {FMC_LA11_N}]
set_property IOSTANDARD LVCMOS18 [get_ports {FMC_LA12_P}]
set_property IOSTANDARD LVCMOS18 [get_ports {FMC_LA12_N}]
set_property IOSTANDARD LVCMOS18 [get_ports {FMC_LA13_P}]
set_property IOSTANDARD LVCMOS18 [get_ports {FMC_LA13_N}]
set_property IOSTANDARD LVCMOS18 [get_ports {FMC_LA14_P}]
set_property IOSTANDARD LVCMOS18 [get_ports {FMC_LA14_N}]
set_property IOSTANDARD LVCMOS18 [get_ports {FMC_LA15_P}]
set_property IOSTANDARD LVCMOS18 [get_ports {FMC_LA15_N}]
set_property IOSTANDARD LVCMOS18 [get_ports {FMC_LA16_P}]
set_property IOSTANDARD LVCMOS18 [get_ports {FMC_LA16_N}]
set_property IOSTANDARD LVCMOS18 [get_ports {FMC_LA17_CC_P}]
set_property IOSTANDARD LVCMOS18 [get_ports {FMC_LA17_CC_N}]
set_property IOSTANDARD LVCMOS18 [get_ports {FMC_LA18_CC_P}]
set_property IOSTANDARD LVCMOS18 [get_ports {FMC_LA18_CC_N}]
set_property IOSTANDARD LVCMOS18 [get_ports {FMC_LA19_P}]
set_property IOSTANDARD LVCMOS18 [get_ports {FMC_LA19_N}]
set_property IOSTANDARD LVCMOS18 [get_ports {FMC_LA20_P}]
set_property IOSTANDARD LVCMOS18 [get_ports {FMC_LA20_N}]
set_property IOSTANDARD LVCMOS18 [get_ports {FMC_LA21_P}]
set_property IOSTANDARD LVCMOS18 [get_ports {FMC_LA21_N}]
set_property IOSTANDARD LVCMOS18 [get_ports {FMC_LA22_P}]
set_property IOSTANDARD LVCMOS18 [get_ports {FMC_LA22_N}]
set_property IOSTANDARD LVCMOS18 [get_ports {FMC_LA23_P}]
set_property IOSTANDARD LVCMOS18 [get_ports {FMC_LA23_N}]
set_property IOSTANDARD LVCMOS18 [get_ports {FMC_LA24_P}]
set_property IOSTANDARD LVCMOS18 [get_ports {FMC_LA24_N}]
set_property IOSTANDARD LVCMOS18 [get_ports {FMC_LA25_P}]
set_property IOSTANDARD LVCMOS18 [get_ports {FMC_LA25_N}]
set_property IOSTANDARD LVCMOS18 [get_ports {FMC_LA26_P}]
set_property IOSTANDARD LVCMOS18 [get_ports {FMC_LA26_N}]
set_property IOSTANDARD LVCMOS18 [get_ports {FMC_LA27_P}]
set_property IOSTANDARD LVCMOS18 [get_ports {FMC_LA27_N}]
set_property IOSTANDARD LVCMOS18 [get_ports {FMC_LA28_P}]
set_property IOSTANDARD LVCMOS18 [get_ports {FMC_LA28_N}]
set_property IOSTANDARD LVCMOS18 [get_ports {FMC_LA29_P}]
set_property IOSTANDARD LVCMOS18 [get_ports {FMC_LA29_N}]
set_property IOSTANDARD LVCMOS18 [get_ports {FMC_LA30_P}]
set_property IOSTANDARD LVCMOS18 [get_ports {FMC_LA30_N}]
set_property IOSTANDARD LVCMOS18 [get_ports {FMC_LA31_P}]
set_property IOSTANDARD LVCMOS18 [get_ports {FMC_LA31_N}]
set_property IOSTANDARD LVCMOS18 [get_ports {FMC_LA32_P}]
set_property IOSTANDARD LVCMOS18 [get_ports {FMC_LA32_N}]
set_property IOSTANDARD LVCMOS18 [get_ports {FMC_LA33_P}]
set_property IOSTANDARD LVCMOS18 [get_ports {FMC_LA33_N}]
set_property IOSTANDARD LVCMOS33 [get_ports {FMC_SCL}]
set_property IOSTANDARD LVCMOS33 [get_ports {FMC_SDA}]
set_property IOSTANDARD LVCMOS33 [get_ports {FMC_PRSNT_M2C#}]
set_property IOSTANDARD LVCMOS33 [get_ports {FMC_TRST#}]

set_property PACKAGE_PIN P5  [get_ports {DP0_M2C_N}]; # GTH8_TX_N
set_property PACKAGE_PIN P6  [get_ports {DP0_M2C_P}]; # GTH8_TX_P
set_property PACKAGE_PIN N3  [get_ports {DP0_C2M_N}]; # GTH8_RX_N
set_property PACKAGE_PIN N4  [get_ports {DP0_C2M_P}]; # GTH8_RX_P
set_property PACKAGE_PIN M5  [get_ports {DP1_M2C_N}]; # GTH9_TX_N
set_property PACKAGE_PIN M6  [get_ports {DP1_M2C_P}]; # GTH9_TX_P
set_property PACKAGE_PIN M1  [get_ports {DP1_C2M_N}]; # GTH9_RX_N
set_property PACKAGE_PIN M2  [get_ports {DP1_C2M_P}]; # GTH9_RX_P
set_property PACKAGE_PIN L3  [get_ports {DP2_M2C_N}]; # GTH10_TX_N
set_property PACKAGE_PIN L4  [get_ports {DP2_M2C_P}]; # GTH10_TX_P
set_property PACKAGE_PIN K1  [get_ports {DP2_C2M_N}]; # GTH10_RX_N
set_property PACKAGE_PIN K2  [get_ports {DP2_C2M_P}]; # GTH10_RX_P
set_property PACKAGE_PIN K5  [get_ports {DP3_M2C_N}]; # GTH11_TX_N
set_property PACKAGE_PIN K6  [get_ports {DP3_M2C_P}]; # GTH11_TX_P
set_property PACKAGE_PIN J3  [get_ports {DP3_C2M_N}]; # GTH11_RX_N
set_property PACKAGE_PIN J4  [get_ports {DP3_C2M_P}]; # GTH11_RX_P
set_property PACKAGE_PIN W3  [get_ports {DP4_M2C_N}]; # GTH12_TX_N
set_property PACKAGE_PIN W4  [get_ports {DP4_M2C_P}]; # GTH12_TX_P
set_property PACKAGE_PIN V1  [get_ports {DP4_C2M_N}]; # GTH12_RX_N
set_property PACKAGE_PIN V2  [get_ports {DP4_C2M_P}]; # GTH12_RX_P
set_property PACKAGE_PIN V5  [get_ports {DP5_M2C_N}]; # GTH13_TX_N
set_property PACKAGE_PIN V6  [get_ports {DP5_M2C_P}]; # GTH13_TX_P
set_property PACKAGE_PIN U3  [get_ports {DP5_C2M_N}]; # GTH13_RX_N
set_property PACKAGE_PIN U4  [get_ports {DP5_C2M_P}]; # GTH13_RX_P
set_property PACKAGE_PIN T5  [get_ports {DP6_M2C_N}]; # GTH14_TX_N
set_property PACKAGE_PIN T6  [get_ports {DP6_M2C_P}]; # GTH14_TX_P
set_property PACKAGE_PIN T1  [get_ports {DP6_C2M_N}]; # GTH14_RX_N
set_property PACKAGE_PIN T2  [get_ports {DP6_C2M_P}]; # GTH14_RX_P
set_property PACKAGE_PIN R3  [get_ports {DP7_M2C_N}]; # GTH15_TX_N
set_property PACKAGE_PIN R4  [get_ports {DP7_M2C_P}]; # GTH15_TX_P
set_property PACKAGE_PIN P1  [get_ports {DP7_C2M_N}]; # GTH15_RX_N
set_property PACKAGE_PIN P2  [get_ports {DP7_C2M_P}]; # GTH15_RX_P

set_property PACKAGE_PIN L7  [get_ports {GBTCLK0_M2C_N}]; # GTH_REFCLK4_N
set_property PACKAGE_PIN L8  [get_ports {GBTCLK0_M2C_P}]; # GTH_REFCLK4_P
set_property PACKAGE_PIN R7  [get_ports {GBTCLK1_M2C_N}]; # GTH_REFCLK6_N
set_property PACKAGE_PIN R8  [get_ports {GBTCLK1_M2C_P}]; # GTH_REFCLK6_P

This approach of defining the DDR interface in the 'part0_pins.xml' file makes sense - the user is not going to redefine the DDR interface.  It is fixed by the HW design.

But this goes back to my original question - why doesn't Trenz provide something similar?  A master XDC and/or a 'part0_pins.xml' file?


JH

#10
November 24, 2021, 06:45:07 AM Last Edit: November 24, 2021, 10:31:12 AM by JH
Hi,

QuoteFirst, they have DDR and some GPIO in the BDF file 'part0_pins.xml'
as I tolled you it's DDR on PL and it's on the module. TE0820 hasn't DDR on PL. PL IOs goes all to the B2B connector and also Bank voltages depends on carrier.
QuoteBut the user would have to comment-out what is not used in the design.
Here is a section of that file.
I don't know which constrains you copy in your last post, but In case you has used it from the UltraZed ,  I wonder where you see an FMC connector on the Module(https://www.avnet.com/wps/portal/us/products/avnet-boards/avnet-board-families/ultrazed/). The XDC must used together with  one of the Avnet carriers. But what's when you use another carrier where it is connected to some other interface or other type of connector? Or simple what's when you use a FMC card which didn't used this IO standards or other VADJ (1.2V,1.8V is allowed for HP Banks) which is defined in this file? In this case you must change whole xdc file completely.

We offer one time the schematics where you can see where everything is connected and we offer also an excel sheet where you get the loc constrains (and you see the connection to different carriers) from an excel sheet:

https://shop.trenz-electronic.de/en/Download/?path=Trenz_Electronic/Pinout
--> 4x5_series_pinout_tracelength.xlsx
IO Standard depends still on the carrier, carrier bank voltage and connected interfaces.


Schematics are available on:
https://shop.trenz-electronic.de/en/Download/?path=Trenz_Electronic/Modules_and_Module_Carriers/4x5/TE0820/REV04/Documents

I would suggest following, use our excel sheet to find loc constrains coordinats (you see also cross reference to carrier connectors in the excel sheet for different carriers) and use Vivado IO Planner to set IOs and IO Standards which you need.

br
John


dm1000

#11
November 25, 2021, 04:40:59 AM
I am not following your last post.

But here is my original question with answers

I have a TE0820 SOM and TE0701 carrier board.

Does Trenz provide a Master XDC file for this configuration?
NO

Or a Git repo of Master XDC files for their boards?
NO

Or a complete 'part0_pins.xml' file in the board definition files or BDF?  I have only found
empty 'part0_pins.xml' files.
Trenz does not provide complete 'part0_pins.xml' files.

The user must generate their own XDC or 'part0_pins.xml' files.   
And that is what I am doing now.

JH

#12
November 25, 2021, 08:43:44 AM
QuoteI am not following your last post.
I'm sorry I couldn't explain that better to you.

QuoteDoes Trenz provide a Master XDC file for this configuration?
NO
This is not quite correct, since we offer this excel:
https://shop.trenz-electronic.de/en/Download/?path=Trenz_Electronic/Pinout
--> 4x5_series_pinout_tracelength.xlsx
--> usable with liblre office and MS office
you can select your TE0820 and your TE0701. Press Update, go to Conn Pin Table and filter "Conn Pin Name" with "FMC" and you get all FMC Pins with corresponding netnames on the carrier, module and the FPGA Pin coordinate.
For example:
FMC Name    ... Modul Net Name... FPGA Pin Name
FMC-LA06_P ... B66_L7_P ... C1   

than simple use text editor like notpad++ an you can add your constrain:
set_property PACKAGE_PIN <Pin from exel sheet> [get_ports {<Name of the port in your design>}];
set_property IOSTANDARD <depends on your FMC Card> [get_ports {<Name of the port in your design>}]

<Pin from exel sheet> --> Pin from the excel sheet in my example C1
<Name of the port in your design> --> must be replaced with the port name on your design. there is no advance for your when I provide you a xdc with:
set_property PACKAGE_PIN C1 [get_ports {LA06_P}]; or set_property PACKAGE_PIN C1 [get_ports {B66_L7_P}]; because you must still change the name
<depends on your FMC Card> -->must be replaced with standard with  is used on your FCM card(can be lvds, cmos....) on this pin and it depends also on VADJ voltage which can be  1.2V and 1.8V on TE0701 with TE0820



QuoteOr a Git repo of Master XDC files for their boards?
NO
correct.

QuoteOr a complete 'part0_pins.xml' file in the board definition files or BDF?  I have only found
empty 'part0_pins.xml' files.
Trenz does not provide complete 'part0_pins.xml' files.
as I told you in this case it makes no sense because PL IOs goes to B2B connector and we don't know what's connected there.

PS setup for QSPI, DDR, USB, ETH, UART...is included on preset.xml and can be load with xilinx board automation.


QuoteThe user must generate their own XDC or 'part0_pins.xml' files.   
And that is what I am doing now.
correct

br
John


Reymon

#13
June 27, 2024, 02:00:26 AM
Hello, I am a beginner FPGA programmer, I tried to do the same, using the XDC file (Vivado 2024.1) to configure the inputs/outputs like I do with Avnet (ZedBoard) or Digilent (Nexys 4) boards. I'm wondering if you successfully created your own XDC or 'part0_pins.xml' files for the TE0820 SOM and TE0701 carrier board. If yes, could you please tell me what procedure you followed?

I have a carrier board TEB0745-02 and TE0745-02-30-1IA SOM.

JH

#14
June 28, 2024, 09:25:47 AM
Hi,
best way is you start with our reference design:
https://wiki.trenz-electronic.de/display/PD/TE0745+Test+Board
It's for Vivado 23.2 and includes Board files for basic PS setting and some petalinux example and also prebuilt binaries to test your HW directly.
I would recommend to use 23.2 when you start, than it's easier to use our reference design with all sources.
For PL IO, you can use AMD IO planner, correct Pin Names are available in our schematics or pinout table. IO Standard for PL IOs depends on your connected periphery (the most pins goes only to simple Pin header).
Pinout table:
https://shop.trenz-electronic.de/de/Download/?path=Trenz_Electronic/Pinout
-->
https://shop.trenz-electronic.de/trenzdownloads/Trenz_Electronic/Pinout/TE0745_series_pinout_tracelength.xlsx

br
John
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