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Porblems with Gigabee Reference MIG project

Started by leo, December 28, 2012, 01:26:55 PM

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leo

Hi all

I've just downloaded reference design TE0600-GigaBee_XC6SLX-MIG-ISE-12.4-v1.0.f79134d.zip

Xilinx ISE reports the following errors:

Quote
ERROR:ConstraintSystem:59 - Constraint <NET  "c1_sys_clk"                       
           IOSTANDARD = LVCMOS33;>
   [mig_v3_61/user_design/par/mig_v3_61.ucf(88)]: NET "c1_sys_clk" not found.
   Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.

ERROR:ConstraintSystem:59 - Constraint <NET  "c1_sys_clk"                       
         LOC = "AA12" ;> [mig_v3_61/user_design/par/mig_v3_61.ucf(138)]: NET
   "c1_sys_clk" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.

Is this design supposed to be used out of the box?

Antti Lukats

#1
Hi Leo,

the answer is mostly described in earlier forum posting:
http://forum.trenz-electronic.de/index.php/topic,245.msg786.html#msg786

first: The MIG project is zipped content of the result of MIG run, it does include all needed files, but it does not include an ISE project for the GUI, the "user design" should be implemented from command-line scripts. This is the way MIG does generate the files. MIG output files are NOT post edited after generation! The ISE project file is not intended to be used as top level project.

If you want to run tools from GUI you need to have new project and include example_top.vhd and all dependancy files, and include ucf example_top.ucf

After doing that you would still get an error with constraint, that is explained in the forum posting I provided link above.

This "reference design" is not meant to be "out of box do something really useful" type of reference, it is mainly provided as starting point to get going with MIG and TE0600. It is assumed that the end user is responsible for implementing some meaningful top level design.

I did run the reference design with 14.3, it did complete without errors, see below:
--

C:\Xilinx\14.3\ISE_DS\ISE\.
   "example_top" is an NCD, version 3.2, device xc6slx45, package fgg484, speed
-2

Analysis completed Fri Dec 28 16:42:45 2012
--------------------------------------------------------------------------------

Generating Report ...

Number of warnings: 0
Total time: 9 secs

Process "Generate Post-Place & Route Static Timing" completed successfully
--

br,
Antti Lukats











leo

Antti,

thanks, I expected something like that. You're right - I do need some top level to implement actual data sending/receiving to MCB

Although from my experience "reference design" should provide several key features which actually make it reference:
1) Has to work out of the box.
2) There should be no any compilation/build errors.
3) All announced features of design has work properly.
This will allow each user to compare this design to his to avoid well known pitfalls.

As for this MIG design - you know, everybody can generate one from Xilinx coregenerator tool. No need to call it reference  ;)

Also, just out of curiosity, when you synthesize MIG with some CPU (e.g. Microblase) do you have timing errors (slacks, component switching limit violations) inside MCB block?
DDR3 requires 320 MHz (which actually becomes 640), and that's kind of boundary frequency for Spartan6. Is that known issue?

Thanks for your support


Antti Lukats

#3
Quote from: leo on December 30, 2012, 07:59:57 AM
Antti,

thanks, I expected something like that. You're right - I do need some top level to implement actual data sending/receiving to MCB

Although from my experience "reference design" should provide several key features which actually make it reference:
1) Has to work out of the box.
2) There should be no any compilation/build errors.
3) All announced features of design has work properly.
This will allow each user to compare this design to his to avoid well known pitfalls.

As for this MIG design - you know, everybody can generate one from Xilinx coregenerator tool. No need to call it reference  ;)

Also, just out of curiosity, when you synthesize MIG with some CPU (e.g. Microblase) do you have timing errors (slacks, component switching limit violations) inside MCB block?
DDR3 requires 320 MHz (which actually becomes 640), and that's kind of boundary frequency for Spartan6. Is that known issue?

Thanks for your support

Hi Leo,

yes, yes and no :) I agree mostly:

1) naming it as "reference design" is probably a "naming issue" - it is more like a MIG coregen reference project, not complete standalone usable reference design.

2) the design is complete UNMODIFIED output from MIG targetting TE600 with both memory cores in use. The problem of not compiling out of box, is more a BUG with the MIG, see the MIG output files SHOULD compile, right? They dont, hence its a bug in the MIG! Now if the generated files are MODIFIED to get them to compile, then once MIG is rerun again by the user the bug may reappear. So I kind of understand why it was left unmodified. Of course this FEATURE should have been documented, saying PLEASE FIX this after MIG generate design!

3) Hm.. I failed to find advertized features :) only that it is MIG based reference design.

Well, basically the design had no documentation at all, not even a feature list, this has to be fixed of course. Sorry for this. This design was offered on customer request, and has been used also in several projects as base reference design. Unfortunately it is not possible to make any of those projects available.

I am playing right now with an idea to have simple AHB wrapper for the MCB, so it would be easy to evaluate the DDR3 with some soft core processors.

br,
Antti Lukats

Antti Lukats

Hi Leo,

I just found my own posting here, with some critical comments regarding MIG and Spartan-6.
Well basically what I said stands, you do not want to experiment with MIG too much if you value your time.

As of timing: Spartan-6 includes hard core Memory controller MCB so the MIG is only generating a wrapper around hard-core. Most of the critical circuitry is inside the hard core, the rest (I/O primitives) are configured by MIG so that the DDR3 memory side PHY timings can be met. There are some more postings about MIG-timing-performance. Ales can probably answer this better, asfaik the S6 memory controller has not much issues - not on the DDR3 PHY side and it is also possible to get very high bandwidth on the user side. For highest possible bandwidth the MCB should be configured as single 128 bit port. Then user clock will be lower for same bandwidth; as this is all implemented in FPGA logic fabric it is more critical to timing. And as member of low cost family FPGA fabric speeds are not that much higher in S6 compared to S3/A series.

After thinking about your project and problems here is my advice:

First please do not even try the MIG approach as starting point,
1) take FULL EDK based reference design
2) build it, test it!
3) enable one additional AXI port and route it out from the design, terminate with dummy signals
4) build and test that still works!
5) Then connect you custom logic or soft core processor to that AXI port in ISE top-level
6) build and test (the MB side first!)
7) test your core...

Sure you will have an "unused microblaze" then, but this will give you a QUICK starting point. Also as a bonus you  can test the memory from microblaze debugger and you can preload the DDR3 as well.

You can convert the design to "microblaze" less one later also, when you have validated that your IP works with DDR3 over AXI bus.

The reason why I am suggesting using AXI forward compatibility with Xilinx 7 series. Only when doing targeted designs for S-6 only it may make sense to use MCB native port interfaces.

br
Antti Lukats

Antti Lukats

Quote from: leo on December 30, 2012, 07:59:57 AM
Antti,

thanks, I expected something like that. You're right - I do need some top level to implement actual data sending/receiving to MCB

Thanks for your support

Hi Leo,

how is going with your design?

Xilinx EDK/XPS has AHB-lite to AXI bridge, so one easy option is to build an system und export AHB-lite for your core.

ARM Cortex-M0 and Cortex-M1 have AHB Lite bus, and I belive Synopsys ARC can also have AHB Lite as bus option. For other buses AHB Lite is probably easier than AXI or MCB to get started.

Antti