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GigaBee Mig

Started by federigi, September 18, 2012, 10:21:20 AM

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federigi

Hi all    :)
I took the GigaBee to use the memory on the module.
I downloaded the file "GigaBee_ISE12.4-MIG".
In the file "memc1_infrastrutture.vhd" and "memc3_infrastrutture.vhd" type of clock used is "DIFFERENTIAL" while GigBee has an input "SINGLE_ENDED."
I would not make a mistake in change these entries and consequently other parts of the program.
And 'A program already changed?

A help would be more than welcome.

thanks Federigi

Ales Gorkic

Hi Federigi,

The files you are referring to are OK. Since these are top level generics you should set them at TOP module. Then the generics are propagated to lower modules.
You have two top modules:
TE060X-GigaBee-Reference-Designs / GigaBee_ISE12.4-MIG / mig_v3_61 / example_design / rtl / example_top.vhd
and
TE060X-GigaBee-Reference-Designs / GigaBee_ISE12.4-MIG / mig_v3_61 / user_design / rtl / mig_v3_61.vhd

At the example_design the clock input was properly defined. But there was an error in mig_v3_61.vhd, which is now fixed.

I strongly suggest not to change the memcX_infrastructure.vhd that you can later upgrade your design.
I suggest that you define the generics properly when instantiating these modules.

Best regards,

Ales

federigi

Hello Alex
Thank you for your concern.

I downloaded and implemented "example_top.vhd."
I launched "Generate Programming File", I returned error:

ERROR: ConstraintSystem: 59 - Constraint <NET
    "memc3_infrastructure_inst/sys_clk_ibufg" TNM_NET = "SYS_CLK3";>
    [C :/ Users/Dino/MigTrenz/trunk/GigaBee_ISE12.4-MIG/mig_v3_61/example_design/pa
    r / example_top.ucf (180)]: NET "memc3_infrastructure_inst/sys_clk_ibufg" not
    found. Please verify that:
    1. The specified design element actually exists in the original design.
    2. The specified object is spelled Correctly in the constraint source file.

Files in Ucf I commented out line 180 and 181

# # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # #
# # Clock constraints
# # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # #
# # NET "memc3_infrastructure_inst/sys_clk_ibufg" TNM_NET = "SYS_CLK3";[/b]
# # TIMESPEC "TS_SYS_CLK3" = PERIOD "SYS_CLK3" 8 ns HIGH 50%; 
# # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # #

In this case, the program file is generated without errors. It 'correct?

* -------------
User Design: Mig_v3_61
This generates error "Implement Design":

ERROR: ConstraintSystem: 59 - Constraint <NET "c1_sys_clk"
ERROR: ConstraintSystem: 59 - Constraint <NET "c1_sys_clk"

I can not find reference to this specific error, do you know something?

I use ISE 14.2 I believe it makes no difference.

Federigi

Ales Gorkic

Hi Federigi,

The commenting you did seems to be OK. The problem was that in UCF there are two timing constraints for two clocks. You need a timing constraint to specify input clock frequency.
We only have one clock input for both MCBs. The net memc3_infrastructure_inst/sys_clk_ibufg was optimized away since it is the same as net memc1_infrastructure_inst/sys_clk_ibufg.

But to be sure I have done it the right way and commited to GIT.

Best regards,

Ales

federigi

#4
Hello Ales
I have problems to implement the latest version of mig.
I'm not an expert in VHDL :(, but I think the program transfers the data in FIFO to fill (64 locations) and then tells me "wr_full." I can not find the  mechanism to write to the DDR, which should download the FIFO.
According qunto reported by UG388 (p. 55) should be automatic when commanded by the arbiter. It 'just that command that I can not locate the file.
Given your experience and you certainly have more influence us, you could not ask "Trenz" to publish the program they use to test your modules "GigaBee"?
Thanks

federigi

Ales Gorkic

Hi Federigi,

This is what we use for testing the boards:
https://github.com/Trenz-Electronic/TE060X-GigaBee-Reference-Designs/tree/master/GigaBee_XPS14.2-FlashWriter

If you are not good at VHDL I do not recommend the MIG project. Interfacing it is not a beginner task.
The EDK projects are easier to handle, especially if you are a good C programmer.

Best regards,

Ales

federigi

Thanks Ales.
I know that the mig is not easy and that is why I ask for help.
The mig I've implemented seems to work regularly with the exception of fifo writing that is not drained. The FIFO is full (64 locations) and generates signal  FIFO is full.
The oprazione data transfer from the FIFO to the dDRAM should be automatic, ie without there being any external commands to be provided (I believe it is the responsibility of the arbitrer).

Best regards,

Federigi

Ales Gorkic

Hi  Federigi,

Each MIG port has three interfaces:
command interface
TX FIFO style interface
RX FIFO style interface

I think you are forgetting to write the command into the command interface.
You need to write for each transaction:
write or read cmd
start address
burst length

As far as i remember that before the first real transaction you need to write in some dummy data that it starts to work properly. 

For more information read http://www.xilinx.com/support/documentation/user_guides/ug388.pdf.

Best regards,

Ales


martinius

Did you progress with the MIG? I am interested in the GigBee too and also need to run a RAM interface.