How to activate the 2nd MCB/DDR3 on TE0600 in EDK ?

[GuinnessTrinker]

I am using a design based on "Recommended starting point for EDK-based designs"
http://www.trenz-electronic.de/download/d0/Trenz_Electronic/d1/TE0600-GigaBee_series/d2/TE0600/d3/reference_designs.html

and EDK 13.2.

I added a lot of devices and everything works fine (until now).

When adding a second S6_MCB for bank #1 I ran into problems.
I used the same configuration as the first MCB (except pins).

What I tried:
1.) just connecting clock-inputs from same signals as the first MCB XPS compiles, but SDK "memory_test" says "failed" on the second DDR3.

2.) Tagging "System Clock BUFPLL" on last config page and connecting "pll_ce*" signals XPS does error.

3.) Adding a new clock_generator (same config as clock_generator_0) XPS error.

Could someone give me a "step by step" instruction please ?

[Ales Gorkic]

Hi GuinnessTrinker,

You probably did not attach AXI bus from processor to second RAM.
I am finishing a new TE0600 reference design which is SW compatible with the current reference design and has dual SDRAM. It was build and tested in EDK 14.2
I have attached system.mhs and system.ucf of this project for your reference.
The full project will be published in a week when we make and test builds for all FPGA sizes.

Best regards,

Ales

[GuinnessTrinker]

I connected the second RAM-Controler to AXI. thats not the fault, but your design helps anyway.
One major fault was that I did not change the default pin-configuration of ZIO and RZQ.

Now have a working design based on XPS 13.2.
My problem: This design is SIMPLE. I had to remove all "my" devices.


Now I can see these differences between your design and mine:

1.) RZQ / ZIO
your schematic: MCB_RZQ_LOC = M19, MCB_ZIO_LOC = C19
your design: MCB_RZQ_LOC = M19, MCB_ZIO_LOC = M16
I think its ok, because we only need an unused pin for ZIO.

2.)
clocks for AXI4, AXI4-lite
your design: AXI4 = AXI4-lite = 62.5 MHz
my design: AXI4 = 100 MHz, AXI4-lite = 50 MHz

3.)
PARAMETER C_MCB_PERFORMANCE = EXTENDED
on 2nd MCB. Cannot be disabled (beside editing system.mhs)


Thoughts:
UG388 figure 3.3 says: "I/O Clock Network To second MCB on same side of device"
Are bank #3 and #1 on the same side ?
Shouldn't we use another BUFPLL_MCB?

[Ales Gorkic]

Hi GuinnessTrinker,

Ad1) The ZIO pin location does not matter.

Ad2) In my design the processor and busses run on the same clock. This way you do not have problems with timing of the CPU.

Ad3) We have VCCint = 1.25V and we can use EXTENDED performance

MCB are in banks1 and 3 and are on the opposite directions. But the clocking I have made is OK and it saves one PLL.

Adding your peripherals from your system.mhs is more or less straightfoward: copy - paste.

Best regards,

Ales

[Thorsten Trenz]

Hi,
please see this Xilinx answer record:
http://www.xilinx.com/support/answers/41520.htm
Do not remove the constraint CONFIG MCB_PERFORMANCE=EXTENDED. Its required by the tools for proper timing.

best regards
Thorsten Trenz

[GuinnessTrinker]

Ok. Thanks for this hint.
Anyway. Even if you remove this line in system.mhs for the second MCB (the first one doesnt have this line), you will ALWAYS get a a file "<project>/__xps/MCB_DDR3_0/mig.ucf" (and MCB_DDR3_1/mig.ucf) which contains "CONFIG MCB_PERFORMANCE= EXTENDED;".
-> You cant disable it in system.mhs.

In the meantime I got a working design with 2* MCBs and all devices.
MicroBlaze is running on 100MHz, AXI4-clock is 100 MHz and AXI4-lite-clock is 50 MHz.

I think it would be a good idea to move both MCB-sections to the top of system.mhs (?).

Thanks for support!