MII on TE0600 GigaBee

[mlefevre]

Hi,

On the TE0600 GigaBee board, to use the PHY (the Marvell Alaska Ethernet PHY chip (88E1111)) embedded on the board:

Is it possible to use the license free Xilinx's IP ethernet_lite 10/100, wich has a MII interface?
Or we necessarily have to buy the Xilinx 's 10/100/1000 Temac soft IP, wich has a GMII interface like the PHY ?

Best regards.

[Ales Gorkic]

Hi mlefevre,

The AXI_ethernet evaluation license means that the MAC in FPGA operates for 8 hours.
Yes it is possible to use the free ethernet_lite 10/100 also.
We have one example of AXI design with this core ported from SP601 board.
https://github.com/Trenz-Electronic/TE060X-GigaBee-Reference-Designs/tree/master/GigaBee_XC6LX-Axi_lite

But unfortunatelly the webserver demo failed to work properly. I suspect that MDIO (serial management interface to PHY) address was not correct, but I could not find the routines for setting this.
Our PHY has different MDIO address (binary 111) with respect to SP601.

Best regards,

Ales

[mlefevre]

Hi,

On the GigaBee_XC6LX-Axi_lite reference design i have noticed that TXCLK pin is located on R11 wich is the location of GTXCLK pin on the PHY.
Don't you should map TXCLK pin on location W12?

Best regards
Mlefevre

[mlefevre]

How the PHY can be "aware" of the acual interface it is dealing with?
I guess by default it is GMII, so we have to configure the PHY in MII.
I suppose this can be done throught the MDIO interface  using

Code Select Expand

int XEmacLite_PhyRead(XEmacLite *InstancePtr, u32 PhyAddress, u32 RegNum,
u16 *PhyDataPtr);
int XEmacLite_PhyWrite(XEmacLite *InstancePtr, u32 PhyAddress, u32 RegNum,
u16 PhyData);
declared in xemaclite.h

But i have no documentation about internal organisation of PHY's registers.
Where can i get such documentation?
The only documentation i have founded about Marvell Alaska Ethernet PHY chip (88E1111) describes the chip pinout.

Best regards
Mlefevre

[Ales Gorkic]

Hi mlefevre,

You are absolutelly right about the TXCLK: the right pin TXCLK  location is W12 as you have found out.
I obviously overlooked this pin when porting the pinout. Thank you for the remark. I have commited the change to github.
That would explain the non working GigaBee_Axi_lite.

As far as I understand the switching on the PHY between the GMII and the MII is done by the MAC.
I have searched the demo project software files for XEmacLite_PhyRead/Write and  there were no hits.
This means that that the PHY registers are not touched.
The PHY CONFIG pins are configured the same on the GigaBee as on the SP601 board (except we have 125MHz clock enabled).
Otherwise the PHY datasheet is under NDA and cannot be freely distributed.

I suggest that you simply replace the TXCLK pin to proper location  and try to run the demo software for the GigaBee_Axi_lite project. It might work out of the box.

Best regards,

Ales

[mlefevre]

Hi,

I have succesfully sent my first UDP frame from the Gigabee board using the xilinx's emacliteIP. Wouhou!!
The problem was not from the phy configuration... no access to PHY internal registers is needed.

Because the FPGA is a spartan 6 no IBUG can be instanciated for PHY_TXCLK and PHY_RXCLK, and according to ds787_axi_ethernetlite.pdf page 33 some constraints must be added on the ucf file.

Code Select Expand

NET "phy_rx_clk" PERIOD = 40 ns HIGH 14 ns;
NET "phy_tx_clk" PERIOD = 40 ns HIGH 14 ns;
OFFSET = OUT 10 ns AFTER "phy_tx_clk" ;
OFFSET = IN 6 ns BEFORE "phy_rx_clk" ;
NET "phy_rx_data<3>" IOBDELAY = NONE;
NET "phy_rx_data<2>" IOBDELAY = NONE;
NET "phy_rx_data<1>" IOBDELAY = NONE;
NET "phy_rx_data<0>" IOBDELAY = NONE;
NET "phy_dv" IOBDELAY = NONE;
NET "phy_rx_er" IOBDELAY = NONE;
NET "phy_crs" IOBDELAY = NONE;
NET "phy_col" IOBDELAY = NONE;
NET "phy_tx_clk" MAXSKEW = 6.0 ns;
NET "phy_rx_clk" MAXSKEW = 6.0 ns;

But this is not enought, i had to make several changes in the Xilkernel and lwIP library Options.
I fact i don't really know what i have done to make it work......

this is my BSP's configuration for the XilKernel and lwIP

Code Select Expand



BEGIN OS
PARAMETER OS_NAME = xilkernel
PARAMETER OS_VER = 5.01.a
PARAMETER PROC_INSTANCE = cpu
PARAMETER STDIN = cpu_debug
PARAMETER STDOUT = cpu_debug
PARAMETER SYSTMR_SPEC = true
PARAMETER SYSTMR_DEV = axi_xil_timer
PARAMETER SYSINTC_SPEC = int_cntrl
PARAMETER CONFIG_PTHREAD_MUTEX = true
PARAMETER ENHANCED_FEATURES = true
PARAMETER CONFIG_YIELD = true
PARAMETER SYSTMR_FREQ = 50000000
PARAMETER SYSTMR_INTERVAL = 1
PARAMETER PTHREAD_STACK_SIZE = 32768
PARAMETER SCHED_TYPE = SCHED_PRIO
PARAMETER CONFIG_TIME = true
PARAMETER MAX_PTHREADS = 8
PARAMETER CONFIG_SEMA = true
PARAMETER N_PRIO = 8
PARAMETER MAX_READYQ = 8
END

BEGIN LIBRARY
PARAMETER LIBRARY_NAME = lwip140
PARAMETER LIBRARY_VER = 1.00.a
PARAMETER PROC_INSTANCE = cpu
PARAMETER N_TX_DESCRIPTORS = 0
PARAMETER N_RX_DESCRIPTORS = 0
PARAMETER API_MODE = SOCKET_API
PARAMETER MEMP_N_TCP_PCB = 4
PARAMETER MEMP_N_TCP_PCB_LISTEN = 1
PARAMETER IP_FORWARD = 1
PARAMETER IP_OPTIONS = 1
PARAMETER ARP_QUEUEING = 0
PARAMETER MEM_SIZE = 16777216
END

Xilkernel works great!!
lwip is a mess full of memory leaks   ....

I am still working on it

mlefevre

[Ales Gorkic]

Thank you mlefevre.

Keep up with the good work.
I have commited the proposed changes to the github project.

Best regards,

Ales

[Oleksandr Kiyenko]

Hi mlefevre,
Can you share your project with us? I start working on it, will be good to start from at least partially working system.
Hope we can help each other working on this project.

Regards
Alex

[mlefevre]

Hi,

I'm sorry. I can't. don't hate me.
The source code is my company's property. I can't share all of it.
But i can still help on some specific problems.
I can maybe share some specifc files like .mhs or .ucf.
The TCP/IP commjunication is now fully integrated in our project so it can't be shared.

Maybe if you send me an email (mathieu.lefevre@augier.com) asking me to help you with TCP/IP communication on Gigabee board.
Maybe my boss will agree to share more.

Good luck.
Mlefevre

[Oleksandr Kiyenko]

Hi
Thanks Mathieu!
Finally I found problem. lwip don't care about PHY auto-negotiation, so if you have Gigabit NIC and auto-negotiation connect to module at "1000", project will not work. Axi_ethernetlite can work only on 10/100.
Latest "tested" project you can found at https://github.com/Trenz-Electronic/TE060X-GigaBee-Reference-Designs/downloads or at
http://www.trenz-electronic.de/download/d0/Trenz_Electronic/d1/TE0600-GigaBee_series/d2/TE0600/d3/reference_designs.html

Regards
Alex

[mlefevre]

Hi,

I didn' have that problem, my compagny's networks is 100Mbit...
But to force the negocation to 100 you can set PARAMETER PHY_LINK_SPEED = CONFIG_LINKSPEED100 of lwip140's parameters in system.mss.

I think that even with a 1Gbit networks the PHY should works at 100 Mbit.

Regards
mlefevre

[Oleksandr Kiyenko]

Hi,
Unfortunately this option don't help. I configure CONFIG_LINKSPEED100 but still see 1000 as auto-negotiation result. So lwip users should care about it. It should be some way to rerun auto-negotiation, will check it when have time, but for today simplest solution I see it's reconfigure NIC to use 10/100 only.

Regards
Alex

[martinius]

A general add:

As far as I know, the PHY has to be configured manually for this if autonegotiation is already completed and the link speed was configured falsely be hardware.

For a current installation I configured the PHy in hardware for eg 1000, and linked it to a 100 switch. No negotiation took place automatically. Only the hw specified config works. (you know the hw config consists of the connection of the LED-out which have to be linked to the propper input pins).

Maybe this is the reason, why it does not work with your 10/100 test.