Problem with usb-driver installation (no IDs provided)

[gelenkeharald]

Hi There,

I've got the TE0300 module and I tried to install the USB drivers. I followed the instruction several times (UM-TE0300-2.pdf and USB Drivers installation), but it won't work.

I connected the module with EEPROM off.
The hardware assistant says, device is unknown (no vendor and device ID provided)
After that I switched EEPROM to ON (nothing changed for the IDs).
I tried to install the "Cypress Generic USB Device" Driver like in this video (http://www.youtube.com/watch?v=NwRuz6Qso9o).
I used the driver (3.4.7.000) from the fresh installed Cypress USB Suite. But after that and any reconnects always the device is not ready and error 10 occurs. What am I doing wrong? Please help me.

GH

[Thorsten Trenz]

Hi,
if there are no vendor and device ID's in device manager, then USB is not working. Best is to sent the module in for inspection.

best regards
Thorsten Trenz

[gelenkeharald]

I solved it. The problem was a broken usb cable. I had to use anotherone this morning and it works....so bad...

By the way there is another problem relating to usb connection. I used the fx2_core to set up the usb communication. I could find some connections between the core-ports with real fpga-pins in the ,,system.ucf" from the reference design and TE0300 schematic, but I don't know how to handle the USB_FD_pin or USB_FD_T, USB_FD_I, USB_FD_O
Is it like that USB_FD_T  is a switch for the tristate data bus? E.g. USB_FD_T is ,,high" then send USB_FD_O and USB_FD_T  is ,,low" then read from bus an write in USB_FD_I?

best regards
GH

[Oleksandr Kiyenko]

Hi gelenkeharald,
Yes you are right about USB_FD_I USB_FD_O and USB_FD_T. If PORT DIR = IO in MHS then EDK generate IOBUF instance for each pin
for example

  
iobuf_11 : IOBUF
    port map (
      I => USB_FD_O(0),
      IO => USB_FD_pin(0),
      O => USB_FD_I(0),
      T => USB_FD_T(0)
    );

But you wrong about polatity. When *_T is '0' *_O drive pin, when *_T is '1' pin state become high-Z (*_O ignored) and it's possible to read data from *_I.

Best regards
Alex

[gelenkeharald]

ok cool thank you
I didn't knew so much about the IO Resources. IOBUF was the word that helped me to find everything in the user guide!
Thank you

[gelenkeharald]

sry another question ;-)
which signals do I have to connect with USB_SCL_pin, USB_SDA_pin, USB_INT0_pin? they don't occur in fx2_core

best regards
GH

[Oleksandr Kiyenko]

Hi gelenkeharald
USB_SCL_pin, USB_SDA_pin, USB_INT0_pin it's i2c bus signals from FX2 microcontroller to xps_i2c_slave core in FPGA.
Microblaze processor reads commands received by i2c bus and execute it (for example run transfer to/from fx2_core).

Regards
Alex

[gelenkeharald]

thank you :-)

ok, I just removed these pins from the system.ucf because I want to set up minimum system with fx2_core

do you know if there exists a mimimum programm to log data in a simple textfile, which were sent by fx2 to the usb at pc?

best regards
GH

[Oleksandr Kiyenko]

Hi  gelenkeharald,
As I understand you want to make some FPGA system which don't use Microblaze processor to control transfers to/from USB (FX2).
Unfortunately we don't have complete solution for this case. You can try to send some data to FX2 endpoint using USB_FIFOADR to select USB endpoint "00"=EP2,"01"=EP4,"10"=EP6,11"=EP8 then read this data using "Cupress USB Control Center" software. (It's easy to find it in Internet).
This way you can read packet by packet in manual mode.

Regards
Alex

[gelenkeharald]

Hi Alexander,

I already downloaded the Control Center, it's part of the necessary Cypress USB Suite.
Where and how can I read packet by packet, what you meant?
The only thing, which is working in Control Center is (with FPGA-reference design).
If I select control endpoint(0x00) --> Data transfer

Bytes to Transfer: 64
Direction: Out
Req Type: Vendor
Target: Device
Req Code: 0xA0 (INITIALIZE)
wValue: 0x0000
wIndex: 0x0000

this is working, but all the other fx2 commands are not working (e.g 0xA1)

best regards

[Oleksandr Kiyenko]

Hi  gelenkeharald,

With USB Control center you can try to run API commands to see how it transferred to and from FX2.
--------------------------
Test #1
Testing API function "Read version".
Read version it's one byte command (code "0x00") - so we can send any packet from 1 to 64 bytes starting with 0x00
to EP1 and should receive 64 bytes response from EP81 it should contain version information at beginning and filled
by 0xFF to the end of packet.
--------------------------
Test #2
Testing FPGA tp PC data stream via EP6.
We can start transfer of test sequence from FPGA to FX2 EP6 by sending command to FPGA.
Command is transfer via I2C interface between FX2 and FPGA. To start test we have to send start
command to USB EP1 which will cause I2C write to FPGA register and start test.
Command layout:
0xAD - Command type I2C write
0x3F - Address (I2C address of Microblaze)
0x0C - 12 bytes to send
0x00
0x00
0x00
0x02 - Start command
Then you have to send stop command which looks the same but last byte will be 0x04 (Stop command) if you will do it from some program you need to add some pause between start and stop commands.
After you send start command you can read data from EP6 (86). 

P.S. We planing to create additional reference project with simple interface from FPGA side which will act as virtual COM port from PC side. Can't give you ETA at the moment.

[gelenkeharald]

Hi Alexander,

I want to thank you for your patience!!!

ok I understand what you mean with Test #1. This is working, of course with the reference design and with my own design, because it doesn't need connection to FPGA.
Test #2 makes no sense for my minimum design with only fx2_core, because I don't have I2C_core.

Which fx2 command do I have to use to read or write into/from the receive/transmit FIFOs of the fx2_core?

Maybe it helps If I describe my whole design. I wrote a core which communicates with an external ADC. If the core receives new data from the ADC, then the transmit fifo is filled with 32 bit data (for testing I fixed the value). After that fx2_core should do the rest (sending 32 bit to fx2). In the simulation (post-route) everything works fine, but I don't know how to handle FX2 from PC side.

best regards
GH

[Oleksandr Kiyenko]

Hi  gelenkeharald,

For you purpose you don't need FX2 firmware commands. In simplest case you should try to send something from FPGA to FX2 fifo and set USB_FIFOADR to EP you need (for example EP6). Then you can try to read from this endpoint using "Control Center". Packets should just go through. The same on other direction - you write from "Control Center" some data to EP and it come to FX2 fifo. Problem is that you don't have: 1) control channel (or you can use packet wrapper to manage packets) 2) Driver - you need some driver to easily access to your data stream.

Regards
Alex

[gelenkeharald]

hi alex its me again ;-)

I had to do some other stuff, but since the last days I could return to my datacommunication project

I solved the problem with sending data from fpga to pc trough the internal fifos of fx2 (I modified the TE0300_API_example), but unfortunatly the other way around seems to be tricky :-/

For testing I installed the cypress driver to have access to fx2 through cyconsole.exe. Here it is also possible to read the data out of the fpga.

I wrote a little core in fpga to receive commands, it looks like that:

Code Select Expand


--commands
constant sample : std_logic_vector(0 to 3) := X"1";
constant set_led : std_logic_vector(0 to 3) := X"F";

    observe_usb_input: process(USB_IFCLK_pin)
    begin
        if(USB_IFCLK_pin'event and USB_IFCLK_pin = '1') then
            if(cnt4rcv < t_rcv) then
                cnt4rcv <= cnt4rcv + 1;
                FIFO_OUT_rd_en <= '0';
            else
                FIFO_OUT_rd_en <= '1'; --read fifo
                cnt4rcv <= 0;
                --interpret received data
                case(FIFO_OUT_dout(0 to 3)) is
                    when sample =>
                    sample_en <= FIFO_OUT_dout(4);
                   
                    when set_LED =>
                    fpga_0_LED_GPIO_d_out_pin <= FIFO_OUT_dout(4);
                    sample_en <= FIFO_OUT_dout(4);
                   
                    when others => null; --no knowing command
                end case;
               
            end if;
        end if;
    end process;


after a defined time (realized with a counter), FIFO_OUT is read and interpret

in cyconsole its possible to write this command through bulk transfer

my problem is, that sometimes the command reaches the fpga and (in this case) the led turns on and sometimes the led is off but it shouldn't

and after a while there is no Bulk OUT Transfer possible, it always fails

some idea what could be wrong? do I have to use the full data length of 512 bytes for endpoint 8? my commands only 4 bytes long, caused by data width of fifo_out

[Oleksandr Kiyenko]

Hi Gelenkeharald,
I understand what you trying to do but your code is look odd for me:
1) You don't check any flags before read ! Your command processing unit can receive trash from empty FIFO or repeat previous command.
2) As for out transfers you should explain how you trying to do it Size of data packet can be anything than less that buffer, no need to fill it. If you want immediate transfer use PKTEND signal.

Regards
Alex

[gelenkeharald]

post deleted

[gelenkeharald]

ahhh I think I'm understanding what you mean with odd ;-)

this solution seems to be smarter ;-)

Code Select Expand


observe_usb_input: process(USB_IFCLK_pin)
begin
if(USB_IFCLK_pin'event and USB_IFCLK_pin = '1') then
if(USB_FLAGD_pin = '0') then --rx fifo isn't empty
FIFO_OUT_ready <= '1';
else
FIFO_OUT_ready <= '0';
end if;
if(FIFO_OUT_valid = '1') then
--interpret received data
case(FIFO_OUT_dout(0 to 3)) is
when sample =>
sample_en <= FIFO_OUT_dout(4);

when set_LED =>
fpga_0_LED_GPIO_d_out_pin <= FIFO_OUT_dout(4);
sample_en <= FIFO_OUT_dout(4);

when others => null; --no knowing command
end case;
end if;
end if;
end process;


[Oleksandr Kiyenko]

Hi Gelenkeharald,
You are going to the right direction!
I see only small piece of code and it's not completed
1) how related FIFO_OUT_ready and FIFO_OUT_valid ?
2) how you reset FIFO_OUT_valid ?
and so on...
you should make complete code and simulate it, then try at hardware

Regards
Alex

[gelenkeharald]

hi alex,

thank you, you're always giving me good hints! Sending commands into the fpga is working perfectly now.

For data generation in fpga I'm using a quite complex structure (because of several analog-digital-converters with different resolution and samplerate), a minimum example is this:

Code Select Expand


vhdl
--datenpakete generieren
process(USB_IFCLK_pin)
begin
if(USB_IFCLK_pin'event and USB_IFCLK_pin = '1' and sample_en = '1') then
cnt_max1119_A_sample_temp <= cnt_max1119_A_sample;
if(cnt_max1119_A_sample /= cnt_max1119_A_sample_temp and chan_en(0) = '1') then --flank detection
detect3 <= '1'; -- is '1' every 50µs
end if;

if(detect3 = '1' and USB_FLAGB_pin = '0') then --tx fifos isn't full
FIFO_IN_valid <= '1';
cnt4sent_max1119_A <= cnt4sent_max1119_A + 1;
case(cnt4sent_max1119_A) is

-- structure for data packets
-- sensor id: 5 bit
-- data_length: 2 bit (01 => 8 bit, 10 => 12 bit, 11 => 16 bit)
-- timestamp: 9 bit
-- data: 16, 12 or 8 bit (rest is filled up with zeros)

when 0 => FIFO_IN_din <= "00001" & "01" & cnt_max1119_A_sample & X"00" & data_s1;
-- when 1 => FIFO_IN_din <= "00010" & "01" & cnt_max1119_A_sample & X"00" & data_s2;
when 1 => FIFO_IN_din <= "00010" & "01" & cnt_max1119_A_sample & X"00" & "10010011"; --just for testing
detect3 <= '0';
cnt4sent_max1119_A <= 0;

when others => null;
end case;
else
FIFO_IN_valid <= '0';
end if;

end if;
end process;


to receive the data, I modified TE0300_API_Example.cpp's ReadData function:

I'm not sure but I think I'm using these TX_PACKET_LEN and packets in wrong way, so that I receive some useful packets with structure as I wanted: "00001" & "01" & cnt_max1119_A_sample & X"00" & data_s1;
but I also receive some trash packets, they are always in hex: "CDCDCDCD" and I don't want them ;-) Do they have a function? where are they come from? Maybe they are related to TIMEOUT_MS of the requested packets?
I also attached my modified ReadData function

Code Select Expand


c++
void LogData(unsigned int handle)
{
int packetlen = TX_PACKET_LEN; //still 102400 from header file
unsigned int packets = 100;
byte * data;
unsigned int total_cnt = 0;
unsigned int errors = 0;
bool printout=true;
int error;

data = new byte [TX_PACKET_LEN*packets]; //allocate memory

//set sampling channels
SendFPGAcommand(handle,0x28); //this function was adapted to fpga-receive-command-module and is working

//start sampling
SendFPGAcommand(handle,0x18);

ElapsedTime.Start(); //StopWatch start
for (unsigned int i = 0; i < packets; i++)
{
packetlen = TX_PACKET_LEN;
if (error = TE0300_GetData(handle, data+total_cnt, &packetlen, PI_EP6,TIMEOUT_MS))
{
printf("ERROR getdata (Packet: %d) : %d", i, error);
errors++;
break;
}
total_cnt += packetlen;
}
TheElapsedTime = ElapsedTime.Stop(false); //DEBUG StopWatch timer

//... commands for writing data into logfile
}



best regards GH

[Oleksandr Kiyenko]

Hi Gelenkeharald,
I am not sure that I understand your goal but will try to make some consumption.
As I understand you trying to pass data by some small packets with various length (or fixed with unused bits filled by zero).
If I going to do such interface I'll do:
1) Packet length should be fixed (there is no visible advantages for small packets to make variable length)
2) You should use PKTEND signal to commit packet to FIFO. Small packet will be collected in internal FX2 FIFO without this signal.
3) packetlen = 4 for your case (As I see you use 4 bytes for transfer maximal packet) to make your packet counter count right -
in your current code it count reads, but you can read more than one packet by one TE0300_GetData call.

as for "CDCDCDCD" - I don't know how it appear - it's more looks like come from your FPGA firmware Driver not processing data from this endpoint - just pass it.

Regards
Alex

[gelenkeharald]

hi alex,

sry maybe my goal was not clear because of big post ;-)

yes I want to sent every 50µs a 4 bytes long package, filled with data from adc, but for testing I implemented just an easy counter, to see if all the packages are arriving in textfile
I was looking for PKTEND signal and noticed that its already right implemented in fx2_core (by the way I'm using v1_50_a), and it works with smaller packages, so I don't have to do something with PKTEND signal?!

I begin to despair, because it won't work on hardware, but in simulation. I always receive different results and loosing data.
Tried to change clocks, packetlenghts, timeout, but no success.

Here is my very minimum vhdl example, its just the fx2 core and a process with generating data every 50µs.

Code Select Expand


----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date:    11:21:36 03/29/2012
-- Design Name:
-- Module Name:    system - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_unsigned.all;
--use IEEE.numeric_std.ALL; --für to_std_logic

use IEEE.NUMERIC_STD.all;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
Library UNISIM;
use UNISIM.vcomponents.all;

entity system is
generic( --hold gibt an wie lange ein sample impuls gehalten wird
t_sample_max1119 : integer := 50000/10; --achtung: doppelte zeit pro kanal (größe in ns)
t_sample_max1119_hold : integer := 200/10
);
  port (
SYS_Clk_pin : in  std_logic;
SYS_Rst_pin : in  std_logic;

-- ChipScope : out std_logic_vector(0 to 31) := (others => '0');

--LED
fpga_0_LED_GPIO_d_out_pin : out std_logic := '0';

--USB Controller
USB_IFCLK_pin : in  std_logic;
USB_SLRD_pin : out std_logic;
USB_SLWR_pin : out std_logic;
USB_FLAGA_pin : in std_logic;
USB_FLAGB_pin : in std_logic;
USB_FLAGC_pin : in std_logic;
USB_FLAGD_pin : in std_logic;
USB_SLOE_pin : out std_logic;
USB_PKTEND_pin : out std_logic:='0';
USB_FIFOADR_pin : out std_logic_vector(1 downto 0); --"00"=EP2,"01"=EP4,"10"=EP6,11"=EP8
USB_FD_pin : inout std_logic_vector(7 downto 0) := (others => 'Z')
    );
end system;

architecture Behavioral of system is

signal SYS_Clk : std_logic;

signal USB_FD_T : std_logic_vector(7 downto 0);
   signal USB_FD_O : std_logic_vector(7 downto 0);
   signal USB_FD_I : std_logic_vector(7 downto 0);

signal Reg_in_0 : std_logic_vector(0 to 31) := (others => '0');
signal Reg_in_1 : std_logic_vector(0 to 31) := (others => '0');
signal Reg_out_0 : std_logic_vector(0 to 31);

signal TX_FIFO_Clk : std_logic := '0';
signal RX_FIFO_Clk : std_logic := '0';
signal USB_RX_Clk : std_logic := '0';

--commands
constant sample : std_logic_vector(0 to 3) := X"1";
constant set_chan : std_logic_vector(0 to 3) := X"2";
constant set_led : std_logic_vector(0 to 3) := X"F";

-- 0x1 --> sample
signal sample_en : std_logic := '0';
signal sample_en_temp : std_logic := '0'; --sample_en flank detection

-- 0x2 --> aktivate chanels
signal chan_en : std_logic_vector(0 to 3) := (others => '0'); -- jedes bit steht für einen adc bzw. eine adc gruppe (max1119_A, max11628, ads8326, max1119_B)


COMPONENT dcm
PORT(
CLKIN_IN : IN std_logic;
RST_IN : IN std_logic;         
CLKDV_OUT : OUT std_logic;
CLKFX_OUT : OUT std_logic;
CLKIN_IBUFG_OUT : OUT std_logic;
CLK0_OUT : OUT std_logic;
LOCKED_OUT : OUT std_logic
);
END COMPONENT;

COMPONENT fx2_core
PORT(
SYS_Clk : IN std_logic;
SYS_Rst : IN std_logic;
Reg_in_0 : IN std_logic_vector(0 to 31);
Reg_in_1 : IN std_logic_vector(0 to 31);
USB_RX_CLK : IN std_logic;
USB_IFCLK : IN std_logic;
USB_FLAGA : IN std_logic;
USB_FLAGB : IN std_logic;
USB_FLAGC : IN std_logic;
USB_FLAGD : IN std_logic;
USB_FD_I : IN std_logic_vector(7 downto 0);
TX_FIFO_Clk : IN std_logic;
RX_FIFO_Clk : IN std_logic;
TX_FIFO_DIN : IN std_logic_vector(0 to 31);
TX_FIFO_VLD : IN std_logic;
RX_FIFO_RDY : IN std_logic;         
Reg_out_0 : OUT std_logic_vector(0 to 31);
Interrupt : OUT std_logic_vector(0 to 7);
USB_SLRD : OUT std_logic;
USB_SLWR : OUT std_logic;
USB_SLOE : OUT std_logic;
USB_PKTEND : OUT std_logic;
USB_FIFOADR : OUT std_logic_vector(1 downto 0);
USB_FD_T : OUT std_logic_vector(7 downto 0);
USB_FD_O : OUT std_logic_vector(7 downto 0);
TX_FIFO_RDY : OUT std_logic;
RX_FIFO_DOUT : OUT std_logic_vector(0 to 31);
RX_FIFO_VLD : OUT std_logic;
ChipScope : OUT std_logic_vector(0 to 31)
);
END COMPONENT;

--fifos
signal FIFO_IN_din : std_logic_vector(0 to 31) := (others => '-');
signal FIFO_IN_ready : std_logic;
signal FIFO_IN_valid : std_logic := '0';

signal FIFO_OUT_dout : std_logic_vector(0 to 31) := (others => '0');
signal FIFO_OUT_ready : std_logic := '0';
signal FIFO_OUT_valid : std_logic;


--max1119-A
signal cnt4max1119_A : integer range 0 to 65536 := 0;
signal cnt_max1119_A_packages : std_logic_vector(0 to 8) := (others => '0'); --package counter
signal cnt_max1119_A_packages_temp : std_logic_vector(0 to 8) := (others => '0'); --flankdetection

signal detect3 : std_logic := '0'; --package generation valid

signal FIFO_OUT_valid_temp : std_logic := '0'; --for FIFO_OUT_valid flank detection

begin

TX_FIFO_Clk <= SYS_Clk; --100 Mhz
RX_FIFO_Clk <= SYS_Clk; --100 Mhz
USB_RX_Clk <= USB_IFCLK_pin; --48 Mhz

Inst_dcm: dcm PORT MAP(
CLKIN_IN => SYS_Clk_pin,
RST_IN => SYS_Rst_pin,
CLKDV_OUT => open,
CLKFX_OUT => SYS_Clk,
CLKIN_IBUFG_OUT => open,
CLK0_OUT => open,
LOCKED_OUT => open
);


inst_fx2_core: fx2_core PORT MAP(
SYS_Clk => SYS_Clk,
SYS_Rst => SYS_Rst_pin,
Reg_in_0 => Reg_in_0,
Reg_in_1 =>Reg_in_1,
Reg_out_0 => Reg_out_0,
Interrupt => open,
USB_RX_CLK => USB_RX_CLK,
USB_IFCLK => USB_IFCLK_pin,
USB_SLRD => USB_SLRD_pin,
USB_SLWR => USB_SLWR_pin,
USB_FLAGA => '0',
USB_FLAGB => USB_FLAGB_pin,
USB_FLAGC => USB_FLAGC_pin,
USB_FLAGD => USB_FLAGD_pin,
USB_SLOE => USB_SLOE_pin,
USB_PKTEND => USB_PKTEND_pin,
USB_FIFOADR => USB_FIFOADR_pin,
USB_FD_T => USB_FD_T,
USB_FD_O => USB_FD_O,
USB_FD_I => USB_FD_I,
TX_FIFO_Clk => TX_FIFO_Clk,
RX_FIFO_Clk => RX_FIFO_Clk,
TX_FIFO_DIN => FIFO_IN_din,
TX_FIFO_VLD => FIFO_IN_valid,
TX_FIFO_RDY => FIFO_IN_ready,
RX_FIFO_DOUT => FIFO_OUT_dout,
RX_FIFO_VLD => FIFO_OUT_valid,
RX_FIFO_RDY => FIFO_OUT_ready,
ChipScope => open
);

bidirectional_bus:
   for i in 0 to 7 generate
   begin
   IOBUF_inst : IOBUF
   generic map (
      DRIVE => 12,
      IBUF_DELAY_VALUE => "0", -- Specify the amount of added input delay for buffer,
                               -- "0"-"12"
      IFD_DELAY_VALUE => "AUTO", -- Specify the amount of added delay for input register,
                                 -- "AUTO", "0"-"6"
      IOSTANDARD => "DEFAULT",
      SLEW => "SLOW")
   port map (
      O => USB_FD_I(i),     -- Buffer output
      IO => USB_FD_pin(i),   -- Buffer inout port (connect directly to top-level port)
      I => USB_FD_O(i),     -- Buffer input
      T => USB_FD_T(i)      -- 3-state enable input, high=input, low=output
   );
 
   end generate;

--Endpoint 6
Reg_in_0(26 to 27) <= "10";
Reg_in_1(26 to 27) <= "10";

--sample_en flank detection
process(SYS_Clk)
begin
if(SYS_Clk'event and SYS_Clk = '1') then
sample_en_temp <= sample_en;
end if;
end process;

--max1119_A sample process (every 50us cnt_max1119_A_packages increases --> generate a package)
process(SYS_Clk)
begin
if(SYS_Clk'event and SYS_Clk = '1') then
if(sample_en = '1' and chan_en(0) = '1') then
if(cnt4max1119_A < t_sample_max1119-1 and sample_en_temp = '1') then
cnt4max1119_A <= cnt4max1119_A + 1;
else
if(cnt_max1119_A_packages = "111111111") then --overflow
cnt_max1119_A_packages <= (others => '0');
else
cnt_max1119_A_packages <= cnt_max1119_A_packages + 1;
end if;
cnt4max1119_A <= 0;
end if;
else
cnt4max1119_A <= 0;
cnt_max1119_A_packages <= (others => '0');
end if;
end if;
end process;


--generate packages
process(SYS_Clk)
begin
if(SYS_Clk'event and SYS_Clk = '1' and sample_en = '1') then
cnt_max1119_A_packages_temp <= cnt_max1119_A_packages;

if(cnt_max1119_A_packages /= cnt_max1119_A_packages_temp and chan_en(0) = '1') then
detect3 <= '1';
end if;

if(detect3 = '1' and USB_FLAGB_pin = '0') then
FIFO_IN_valid <= '1';
--4 byte package
FIFO_IN_din <= "00001" & "01" & cnt_max1119_A_packages & X"00" & "10010011";
detect3 <= '0';
else
FIFO_IN_valid <= '0';
end if;

end if;
end process;

--process for receiving and interpreting external commands
observe_usb_input: process(USB_IFCLK_pin)
begin
if(USB_IFCLK_pin'event and USB_IFCLK_pin = '1') then
FIFO_OUT_valid_temp <= FIFO_OUT_valid;
if(USB_FLAGD_pin = '0') then --rx fifo isn't empty
FIFO_OUT_ready <= '1';
else
FIFO_OUT_ready <= '0';
end if;
if(FIFO_OUT_valid = '1' and FIFO_OUT_valid_temp ='0') then --rising edge
--interpret received data
case(FIFO_OUT_dout(0 to 3)) is
when sample =>
sample_en <= FIFO_OUT_dout(4);
fpga_0_LED_GPIO_d_out_pin <= FIFO_OUT_dout(4);

when set_chan =>
chan_en(0 to 3) <= FIFO_OUT_dout(4 to 7);

when set_LED =>
fpga_0_LED_GPIO_d_out_pin <= FIFO_OUT_dout(4);

when others => null; --no knowing command
end case;
end if;
end if;
end process;

end Behavioral;


with TX_PACKET_LEN = 4 and packets=10 I expect
1. "0A 01 00 93"
2. "0A 02 00 93"
3. "0A 03 00 93"
4. "0A 04 00 93"
5. "0A 05 00 93"
6. "0A 06 00 93"
7. "0A 07 00 93"
8. "0A 08 00 93"
9. "0A 09 00 93"
10. "0A 0A 00 93"

but there are 3 different types of results I get
first: datatransfer with less errors (of TE0300_GetData) than packets
1. "0A 01 00 93"
2. "0A 02 00 93"
3. "0A 03 00 93"
4. "0A 08 00 93"
5. "0A 0A 00 93"
6. "CD CD CD CD" (error: 31)
7. "CD CD CD CD" (error: 995)
8. "CD CD CD CD" (error: 995)
9. "CD CD CD CD" (error: 995)
10. "CD CD CD CD" (error: 995)

second: datatransfer with no errors
1. "0A 01 00 93"
2. "0A 02 00 93"
3. "0A 05 00 93"
4. "0A 0A 00 93"
5. "0A 0F 00 93"
6. "0A 14 00 93"
7. "0A 19 00 93"
8. "0A 1E 00 93"
9. "0A 23 00 93"
10. "0A 22 00 93"

and third: datatransfer completely failed
10 times error: 995 occurs

conspicuous is beside the indeterministic behaviour, that if data is transferred, some of the packets are lost

do you maybe have got a minimum example or something like that? I really don't know how to solve this problem :-(

[Oleksandr Kiyenko]

Hi Gelenkeharald,
It's really hard to find your problem without serious simulation and testing on hardware, unfortunately I don't have time for that.
We are planing to make some simple reference project which don't use microblaze processor to control USB transfers, but think that this project will have other FX2 firmware and driver. Will inform you any news in this case.

Regards
Alex

[gelenkeharald]

hi alex,

thank you for this information and your help anyway. I'm trying to use the new libraries on GitHub, maybe it helps.

best regards GH

[Hengist]

The release of the third generation Trenz Electronic USB FX2 Suite made this post obsolete. Please access current documentation and resources here: TE USB FX2 Suite.