TE0300DLL.dll question

[gelenkeharald]

Hello guys,

this is me again...I'm still working at this problem and didn't found a solution :-(. I just builded up a new project, with just the fresh fx2_cores, ucf file form reference design, fifos, dcms and a connection from rx_fifo to tx_fifo. So the system should receive the same data as sent to fpga (it is very close to the reference). But even this is not working. I receive not the same bytes as I sent, but always the same trash:
in: various 4 bytes --> out: d f0 ad ba

this is my loop function in c++

Code Select Expand


void Loop(unsigned int handle)
{
byte * data_in;
data_in = new byte [4]; //allocate memory
byte * data_out;
data_out = new byte [4]; //allocate memory
int error;
int packetlen;

data_in[0] = 0xFF;
data_in[1] = 0xFF;
data_in[2] = 0xFF;
data_in[3] = 0xFF;

packetlen = 4;

if (error=TE0300_SetData(handle, data_in, 4, PI_EP8))
{
printf("ERROR SetData: %d\n", error);
}

if (error = TE0300_GetData(handle, data_out, &packetlen, PI_EP6,TIMEOUT_MS))
{
printf("ERROR GetData: %d\n", error);
}

printf("1: %x --> %x \n", data_in[0], data_out[0]);
printf("2: %x --> %x \n", data_in[1], data_out[1]);
printf("3: %x --> %x \n", data_in[2], data_out[2]);
printf("4: %x --> %x \n", data_in[3], data_out[3]);

delete data_in;
delete data_out;
}


I uploaded my minimum design: I ask you friendly to have a short look over it, please. It would really really help me. I absolutly don't know how to proceed.


http://www.4shared.com/zip/1F3uZLGg/fx2_engine.html


some more information:
I'm using this firmware: http://www.trenz-electronic.de/fileadmin/docs/Trenz_Electronic/TE-USB-Suite/firmware/version_3/TE_USB_FX2-v03.00.iic
and this driver: http://www.trenz-electronic.de/fileadmin/docs/Trenz_Electronic/TE-USB-Suite/drivers/version_2/TE03xx-USB_32-64.zip

in addition: here is an very detailed instruction what I've done

-create new project
-add fx2_core.vhd and fx2_core.ucf (from latest reference design)
-add libraries proc_common_v3_00_a and xps_fx2_v1_50_a
-add dcm_sys with clkin 125 Mhz and clkfx 100 Mhz
-add dcm_usb with clkin 24 Mhz and clkfx 48 Mhz
-change parameter C_RX_FIFO_KBYTE = 2 to have rx fifo
-add tx_fifo: independent clocks, block ram, first-word-fall-through, write_width: 32, read_width: 8, write_depth: 8192, flags, write_data_count: 13
-add rx_fifo: independent clocks, block ram, first-word-fall-through, write_width: 8, read_width: 32, write_depth: 4096, flags, read_data_count: 10
-create system.vhd: adding all components, instantiating all components, connecting FIFO_IN_din with FIFO_OUT_dout

Many thanks in advance

best regards GH

[Oleksandr Kiyenko]

Hi gelenkeharald,
I check your project and see several design mistakes:
1) you assigning LE vectors to BE vectors

...
constant EP6ADR         : STD_LOGIC_VECTOR( 1 downto 0) := "10";
...
Reg_in_0(26 to 27) <= EP6ADR;
..

It's not good practice. Xilinx ISE allow such assignments but other synthesis tools not (there is no considerations for such assignment).
2)

add tx_fifo: independent clocks, block ram, first-word-fall-through, write_width: 32, read_width: 8, write_depth: 8192, flags, write_data_count: 13

in reference project tx_fifo type - Standard FIFO
3) your code is wrong !

observe_usb_input: process(SYS_Clk)
   begin
      if(SYS_Clk'event and SYS_Clk = '1') then
         rx_fifo_rst <= '0';
         if(FIFO_OUT_valid = '1') then
            if(initialize = '0') then
            initialize <= '1';
               if(FIFO_OUT_dout /= X"FFFFFFFF") then --initializing command
                  rx_fifo_rst <= '1';
               end if;
            else
               FIFO_IN_din <= FIFO_OUT_dout;
               FIFO_OUT_ready <= '1';
            end if;

         elsif(FIFO_OUT_ready = '1' and FIFO_IN_ready = '1') then
            FIFO_IN_valid <= '1';
            FIFO_OUT_ready <= '0';
         else
            FIFO_IN_valid <= '0';
         end if;
      end if;
   end process;

if you will have received data packet in rx_fifo (not a single word)
only last word will go to tx_fifo

In future please SIMULATE your project BEFORE ask somebody to help you.

P.S. Please don't use sharing services which require registration to download - nobody like it.

Regards
Alex

[Horsa]

This is a known issue for 32 bit version. We are investigating.

With the kind support of a Cypress engineer, we could fix the problem, due to includes issues we could not find any official documentation for.
  http://www.cypress.com/?app=forum&id=167&rID=64182
We will push the fixes by tomorrow in GitHub.

[gelenkeharald]

hi alex,

thank you for checking my project, please excuse for my design mistakes and sharing service problem.

I made some progress. Can send data to fpga and receive the same packages. But I still have some understanding problems. I guess there are some timing problems in the project.

I only wanna ask you some understanding questions:

First: TIMESPEC TS_USB_IFCLK_pin = PERIOD USB_IFCLK_pin 20833 ps; from fx2_core.ucf
how does that fit together with the oscillator frequency? I remember I asked you the same questions some weeks ago, but it still doesn't make sense for me.

Let me explain what I understand and please correct me, if I'm wrong.
oscillator frequency: 24 Mhz
is routed to fpga USB_IFCLK_pin and fx2 (the pin name is not important), so that means fx2 and fx2_core module are running with the same clock
24 Mhz or 48 Mhz?
24 Mhz: I don't need a dcm in fpga for USB_IFCLK_pin, but then constrain is wrong!
48 Mhz: I have to use a dcm in fpga for USB_IFCLK_pin to double 24 Mhz external clock! contrain is right!
So what is right?

Second: Another thing is reaching the contraints:
I clocked OUT all the signals from fpga to fx2

Code Select Expand


process(USB_CLK)
begin
if(USB_CLK'event and USB_CLK = '1') then
USB_SLRD_pin <= USB_SLRD;
USB_SLWR_pin <= USB_SLWR;
USB_SLOE_pin <= USB_SLOE;
USB_PKTEND_pin <= USB_PKTEND;
USB_FIFOADR_pin <= USB_FIFOADR;
USB_FD_I <= USB_FD_I_temp;
USB_FD_T <= USB_FD_T_temp;
USB_FD_O <= USB_FD_O_temp;
end if;
end process;

the result, deterministic behaviour of data transfer, but the problem with 1 byte shifted packages

Then I tried to clock in the other signals from fx2 to fpga, but I get inadmissible signal assignment (X) in behavioral simulation

Code Select Expand


process(USB_CLK)
begin
if(USB_CLK'event and USB_CLK = '1') then
USB_FLAGA <= USB_FLAGA_pin;
USB_FLAGB <= USB_FLAGB_pin;
USB_FLAGC <= USB_FLAGC_pin;
USB_FLAGD <= USB_FLAGD_pin;
end if;
end process;


Do I have to clock in these signals? Is it right to clock USB_FD_I, USB_FD_O, USB_FD_T, too? Did I clocked them right?
the addition temp is to show that this signal isn't synchronized to USB_CLK ( USB_FD_T_temp and  USB_FD_O_temp from fx2_core;  USB_FD_I_temp from iobuf)

Thank you

best regards
GH

[Oleksandr Kiyenko]

Hi gelenkeharald,

Let me explain what I understand and please correct me, if I'm wrong.
oscillator frequency: 24 Mhz
is routed to fpga USB_IFCLK_pin and fx2 (the pin name is not important), so that means fx2 and fx2_core module are running with the same clock
24 Mhz or 48 Mhz?
24 Mhz: I don't need a dcm in fpga for USB_IFCLK_pin, but then constrain is wrong!
48 Mhz: I have to use a dcm in fpga for USB_IFCLK_pin to double 24 Mhz external clock! contrain is right!
So what is right?

24MHz from clock oscillator -> FX2 (inside FX2 chip PLL module multiply this frequency x2) -> 48 MHz at USB_IFCLK_pin -> FPGA
You don't need to clock USB interface input or output signals - it's already done inside fx2_engine.vhd when needed. Adding this clocking you shift control signals timing. As core made to reach maximum possible bandwidth, it don't have wait states so your code destroy internal logic. The same right for FD pins. Just connect it to external pins - no extra logic required.

Regards
Alex

[Hengist]

The release of the third generation Trenz Electronic USB FX2 Suite made this post obsolete. Please access current documentation and resources here: TE USB FX2 Suite.