Trenz Electronic Products > Trenz Electronic FPGA Modules

Xilinx Board Description file (*.xbd2) for GigaBee XCSLX (UM-TE0600)

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GuinnessTrinker:
Hi,
would you please be so kindly to provide such file(s)?
If so, users/customers could easily create BSB projects like they can do with Xilinx evaluation boards.

(unsymmetrical clock, fixed pll-locations for MIG, fixed MAC-address, .ucf file, ..)

Thanks in advance

Oleksandr Kiyenko:
Hi  GuinnessTrinker,

You can get BSB files from Github repository.
https://github.com/Trenz-Electronic/TE-BSB
Note that this project is under active development.

Regards,
Alex

GuinnessTrinker:
Thanks for that.

You are right. The development is not finished, but it is helpful.

I still have to edit some settings:

1.) ports clk_p, clk_n -> sys_clk (unsymmetrical)
2.) port address of TEMAC: 0b00001 -> 0b00111
3.) MIG/FPGA options: ZIO pin -> Y2
4.) copy .ucf to system/data (With Xilinx-boards this is done when exporting the project from XPS)
5.) modify system.mhs: sys_clk: delete  "DIFFERENTIAL_POLARITY = P,"

The TE0600 board is missing in your docs folder.
My project is based on AXI. I think PLB is outdated.
I use ISE 13.4.

Regards

RDT2:
I concur. The XBD2 / IP-AXCT files should be provided for both the 600 alone and with carrier board 603. A complete UCF file should also be provided for all of the pins/devices already utilized on the 600/603.

reLinux:

--- Quote from: GuinnessTrinker on April 03, 2012, 08:14:50 AM ---Thanks for that.

I still have to edit some settings:


--- End quote ---

Hello GuinnessTrinker

did you succeed to build a AXI Microblaze? I just tried to build a minimal one for several hours without success.

SDK keeps saying either that Microblaze is in reset state or that the debug module cannot be accessed.

I am using a HS1 JTAG programming cable.

Kind regards

Stephan

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