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problem with behavioral simulation of fx2_core

Started by gelenkeharald, March 09, 2012, 11:31:26 AM

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hi guys,

I tried to build up a minimum usb communication system with the fx2_core (folder xps_fx2_v1_10_a) as described several times in other threads. Primarily I want to simulate the whole core including the tx_fifo, tx_fifo_addr and rx_fifo, because I want to ensure that everything works. Then I would like to add my specific code. So I built a testbench for the fx2_core behavioral simulation. My problem ist, that all the internal signals for a communication between the tx_fifo and the usb_fd_o port are being set in (my opinion) right way, but there is no output at usb_fd_o port.

Let me describe my way and results.

my stimulus process looks like this
SYS_Rst <= '1';
wait for 100 ns;
SYS_Rst <= '0';
wait for 100 ns;

        wait for SYS_Clk_period;
TX_FIFO_VLD <= '1';
USB_FLAGC <= '1';
USB_FLAGD <= '1';

In the simulation you can see:
- tx_fifo is ready after SYS_Rst goes "low"
- tx_wr_en goes "high" after tx_fifo_vld and the flags have been set
- one cycle of usb_ifclk, fifo2fx2_state goes "01" (write state) and tx_rd_en goes "high"

so what happens? what is wrong? seems to be no signal from the fifo cames out of the block, because all the tx_fifo flags (e.g. full, empty, overflow...) are the whole simulation "low"

I'm really thankful about any help.

Cheers Rob

Oleksandr Kiyenko

Hi Rob,
At first look you need also drive USB_FLAGB - it's tx full flag so you should set
USB_FLAGB <= '0';
to enable write transaction.



ahm damn, I forgot to attach the simulation results
than you would have seen that I already set USB_FLAGB <= '0'

here are the pictures

Oleksandr Kiyenko

Hi Rob,
Looks like you have problems because of wrong tx_fifo model. For example usb_slwr signal is produced from
tx_fifo_valid signal at your model it's not connected. Also tx_fifo_vld signal should go high only after read from fifo
(cycle after tx_fifo_out_en_i was high).
Also xps_fx2_v1_10_a it's old core, current one it's xps_fx2_v1_50_a it's little slower at PC -> FX2 transfers, but
works on all FX2 chips (come FX2 chips have some timing issue which cause errors in PC -> FX2 burst transfers)
this core not used special FIFO signals so easier to simulate.


hi alexander,

thank you for your help, where can I get the new version of the fx2_core?
I used 1_10_a, because its part of the reference design

hopefully my project works with the new version

thank you


it's me again

I downloaded the new xps_fx2_v1_50_a from the source you gave me. Then I searched for the xilinx project file and found it in the "devl/projnav" folder. I started the new project. With new source --> ip --> fifo I generated the three fifos. After I tried so simulate with the same testbench ( I only had to change a few things: e.g. new wordwidth for usb_fd_t), but unfortunatly I received the same (no) results.
Maybe my problem is in generating the cores? I'd like to describe my proceeding more in detail, to figure out what I'm doing wrong.

e.g. tx_fifo generation:
- independent clocks/block ram
- first-word-fall-through
- write width: 32
- write depth: 4096
- read width: 8
- overflow/underflow/valid flag
- use extra logic for more accurate data counts
- write data count width: 13
everything else let to default

also interesting are the warning messages after isim simulator
I'm starting to think, I understood something totally wrong ;-)

Oleksandr Kiyenko

Hi Rob
devl/projnav it's old obsolete folder not used in current version. I remove it to not confuse you.
All used fifo cores generated via scripts. Easiest way to generate it it's add xps_fx2_v1_50_a
core to EDK project and run "Generate netlist" after that you can take all files you need from
"implementation/xps_fx2_wrapper" (where xps_fx2 it's name of core). No need to run coregenerator
XPS will do it right way.



Hi Alex,

first of all, thank you very much for your patience!

But how can I generate the fifos with scripts in ISE? I have no licence for the EDK, otherwise I would have used the reference design and added my stuff there ;-)

I really don't know why the fifos not working with the core, because a testbench including only the fifos is working!


Oleksandr Kiyenko

Hi Rob,
Don't know what can be wrong in your simulation.
I attach wrapper files. In verilog files you can find coregen parameters.
Compare it with your and maybe you will find some difference.
Or you can use just one file fx2_engine with your FIFOs it provide clear FIFO interface which easier to debug.