Playing ZX Spectrum in HDMI in MAX1000 support SDHC 32Gbytes

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Playing great new games:
https://itch.io/s/111036/full-pat-morita-pack

Capture playing Shovel Adventure:
https://youtu.be/uP6nl9aS-cw

New 4Mbytes Sdram to Sram Wrapper:
https://github.com/AtlasFPGA/zx/blob/main/atlas.max/sdram.v

New DVI/HDMI Wrapper in verilog:
https://github.com/AtlasFPGA/zx/blob/main/atlas.max/hdmi.v

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And playing some new demos:
"Elysium State"

"In Color by Darklite and Offence"

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Tutorial, how to port some VHDL opensource cores from reverse U16 - Spanish - you can use translation.

It is a great excersise to knwo how to deal with the VHDL program language and you can see it here.

In next videos I'm going to share how to deal with the serilizer, because MAX10, has a diferent serializer than cyc1000.

In this case i share the ZX48 implementation in VHDL as a .QAR proyect:
https://github.com/AtlasFPGA/U16_ZX_48_Spectrum_Reloj_50MHZ_VHDL

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Using an DVI signal in 24bit color an late runs a ZX Spectrum.

The demo is located here for CYC1000, adapt it to MAX1000, is fairly easy.
https://github.com/AtlasFPGA/Demo_PIOTR.GO_888_DVI

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This is the lines for using the DVI signal, the max 10 with a 55 nanometer achive the frecuencies of a DVI/Digital_video with no problem.

Code Select Expand

set_location_assignment PIN_H6 -to SYS_CLK
set_location_assignment PIN_H5 -to TMDS[0]
set_location_assignment PIN_K10 -to TMDS[1]
set_location_assignment PIN_H13 -to TMDS[2]
set_location_assignment PIN_J13 -to TMDS[3]
set_location_assignment PIN_K11 -to TMDS[4]
set_location_assignment PIN_K12 -to TMDS[5]
set_location_assignment PIN_J12 -to TMDS[6]
set_location_assignment PIN_L12 -to TMDS[7]

You can see the pin planner in the photo added.
It is a nice thing to have a 24 or 30 bit color scheme an consumes a very low count kles.
There is a screenshot also of the compiled piotr-go-vga, but consumes only 8 pins.
In order to reproduce a vga signal with 24bits.
You need:

8 Pins -> Red
8 Pins -> Green
8 Pins -> Blue
1 Pin -> Horizontal Sync
1 Pin -> Vertical Sync

This is the minimal signals you need in vga 8+8+8+1+1=26, but in a digital signal only uses 8 signals, the wrapper used could give 30bits but the implementation only gives 24bits, so 2 signals added for each RGB Color signals.
So for max1000 is more suitable a digital video signal.



You can see the impact in the utilization by entity of using a video signal compatible with DVI.

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With the previous DVI/HDMI pins and the master clock we can create an interesting gradient of color. At a resolution of 1280x1024.

You can translate from this vídeo. I converted the sources from CYC1000 to MAX1000.

The only you need is a HDMI-PMOD, and connect the digital signals with dupont cables.
We need only 8 cables for a DVI/HDMI signal.

I add the sources also for MAX1000.

HDMI-PMOD:


HDMI-SIGNALS:


SCREEN-MAX1000:


SOURCES:
DVI_1280x1024_MAX1000.zip

ORIGINAL SOURCES:
https://github.com/open-design/max10_hdmi/tree/master

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We will rename the signals of the implementation, that uses 24bits of color created by Piotr.go.

Code Select Expand

https://github.com/piotr-go/Lichee-Tang/blob/master/VGA/src/vga.v
To the nomenclature in the previous demo/hdmi demo DVI_1280x1024_max1000.

We visualize the files *.qsf.

VGA.QSF signals:

Code Select Expand

set_location_assignment pin_h6 -to SYS_CLK
set_location_assignment pin_h5 -to TMDS [0]
set_location_assignment pin_k10 -to TMDS [1]
set_location_assignment pin_h13 -to TMDS [2]
set_location_assignment pin_j13 -to TMDS [3]
set_location_assignment pin_k11 -to TMDS [4]
set_location_assignment pin_k12 -to TMDS [5]
set_location_assignment pin_j12 -to TMDS [6]
set_location_assignment pin_l12 -to TMDS [7]

Max10_50.qsf signals:

Code Select Expand

set_location_assignment pin_h6 -to clk12Hz
set_location_assignment pin_h5 -to tmds [0]
set_location_assignment pin_k10 -to tmds [1]
set_location_assignment pin_h13 -to tmds [2]
set_location_assignment pin_j13 -to tmds [3]
set_location_assignment pin_k11 -to tmds [4]
set_location_assignment pin_k12 -to tmds [5]
set_location_assignment pin_j12 -to tmds [6]
set_location_assignment pin_l12 -to tmds [7]

I have made the change of TMDS and SYS_CLK to tmds and CLK12MHz names.

Now change the integrated FPGA.
I proceed to eliminate one by one the assignments of the pins, in pin planner.

I do that because, I want to see the name of the signals.
Let's see if Arrow Blaster is detected.
Appears:

Code Select Expand

USB serial Converter A
USB Serial Converter B

Once the first compilation is finished we enter Pin Planner.
And we see if the name of the signals have been changed.

Next, we will go to all the signs and rename them since we have taken the terminology of the DVI_1280x1024_max1000 screen.
And once the assignments have been changed again, we will proceed to send the flow of data to the Max1000.
And see if the capturer shows the screen_exercise of Piotr.go.

As the signals are seen, they have been renamed, and use the same nomenclature as in the previous screen_exercise.
Once the correspondences of the signals and the pins we rebuilt.

Let's take a walk through the VGA.V file

We will send the data flow to the Max1000.

This exercise is very interesting since it shows how starting from a 640x480 VGA signal with a 60Hz vertical sync.
That makes a 25,175 pixel clock, we visualize the screen at full 24 bits colors, with only 8 HDMI pins.

We will visualize the black box of PPL from intel/altera in the Max 10 family.
We start with a clock from 12MHz.
We approximate by PLL limitations the 25,175MHz Pixel Clock frequency at 25,20000000MHz.
HDMI frequency is 5 times the frequency of pixel clock; that is a 126.00000000MHz Clock.
We visualize that in the Used PLL we could still generate three other frequencies C2, C3. and C4.

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Having already created two different screensaver implementations, we used a VT52 terminal. If you look at the upper left corner, you'll see the seconds. They are slightly faster since, for better visualization in DVI(HDMI, we set a clock of 50.40 MHz, The design uses at first a 50MHz clock as the initial design frequency.

ATLAS Sources:
https://github.com/AtlasFPGA/vt52

Intel/Altera's intellectual properties, such as the phase-locked loop or "PLL," have been approximated to a pixel clock of 25.2 MHz, which gives a resolution of 640x480 with 60Hz vertical synchronization, the exact clock is 25,175Mhz.

You will typically encounter the following errors if you start from a CYCLONE design in families I through IV.
Typically, projects have this configuration:
Single Uncompressed Image (912Kbits UFM)

Let's view the error:
"16031 Current Internal Configuration mode does not support memory initialization or ROM.
Select Internal Configuration mode with ERAM."

This is a memory initialization error.

Now we apply the address and change the parameters.
Assignments - Device - Device and Pin Options - Configuration - Configuration Mode: Single uncompressed image with Memory Initialization
Translate.

The design compilation has been successful.
It is very important that the "IP" intellectual property rights are transferred to the MAX 10 family, given that we have a Max1000 SuperCPLD/FPGA.

Let's begin programming.
And we'll see how the VT52 terminal design shows the seconds of activity in the upper left corner.

I'm slowly translating the comments into other languages.
Greetings.

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Let's move the VT105 pin to the MAX1000 pinout, from the CYC1000 one, step by step.

Original sources:
https://pdp2011.sytse.net/wordpress/pdp-11/

Sources with the first wrapper and for the CYC1000 pinout:
https://github.com/AtlasFPGA/vt105_2023_PDP11/tree/main

First, we check if the description is correct, if it compiles, and if it doesn't generate errors.

We proceed to change the FPGA chip to the SuperCPLD MAX 10 family, i.e., the MAX1000 10M08SAU169C8G.
We compile so that it detects the design signals and then we perform the signal-to-pin assignment one by one from the text file.
We correctly place the corresponding pinout for the MAX1000 pin.

As for the serial port, I'm going to make a crossover, putting TX where RX is, on the ATLAS board.
There are two serial ports; the one I'm going to use as the main one is the one associated with the FTDI FT2232H.

Once compiled, you'll see that there's enough space. This includes both the number of logic elements used, the number of registers, and the block memory "BRAM."

Note that the user flash memory blocks "UFM" and the ports for sampling analog signals "ADC" have not been used.

I open Pin Planner.
I proceed to assign pin to pin.

Let's see if they are really crossed. To do this, go to the ATLAS website and look at the ports associated with the CYC1000 twin board to compare the serial port configuration.

We see the assignments. There are two possibilities for CYC1000 in the VT100 or VT105 terminal configuration: using a serial port directly via pins or using the FT2232H. To switch, uncomment whether you want UART1 and UART2.

We see that they are swapped where RX is, so TX should be placed:
We see that they are swapped where RX2 is, so TX2 should be placed:
#set_location_assignment PIN_R7 -to rx
set_location_assignment PIN_R7 -toTX ##Transmitter output of FT2232H (Tx) 3.3 V - THIS IS SWITCHED TO RX

Then we are doing it correctly by crossing TX with RX for both UART1 and UART2.
Let's adjust the frequencies to more precise ones to see if the VT105 terminal displays.

I disconnect the Max1000 SuperCPLD.
The default description I have for one of the two internally hosted data streams is 24-bit display.

We swapped the HDMI wrapper; the first has less color depth and cannot carry sound.
The one we implemented can carry sound and also has 24-bit support, but only uses almost 2000 logical elements or "kles."

After having several errors, the first one caused comments with // and the second one when assigning signals in the wrapper.
The signals in both wrappers are practically identical, which is the great advantage of using VHDL.

We added the signal-to-pin correspondence.
In TMDS format, from 0 to 7.

We now have a VT105 terminal on the RX and TX ports of the FTDI FT2232H, in my MAX1000.

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Counter at 1280x720, in which virtual LEDs are generated, and the upper octet of the red ones.
They are redirected to the LEDs present on the MAX1000.
The compilation generates these results.

Flow Status Successful - Tue Apr 01 18:25:45 2025
Quartus Prime Version 17.1.0 Build 590 10/25/2017 SJ Lite Edition
Revision Name max10_50
Top-level Entity Name hdmi_leds
Family MAX 10
Device 10M08SAU169C8G
Timing Models Final
Total logic elements 358 / 8,064 (4%)
Total registers 219
Total pins 19 / 130 (15%)
Total virtual pins 0
Total memory bits 0 / 387,072 (0%)
Embedded Multiplier 9-bit elements 0 / 48 ( 0 % )
Total PLLs 1/1 (100%)
UFM blocks 0 / 1 ( 0 % )
ADC blocks 0 / 1 ( 0 % )

It's important to note that the number of memory blocks is zero.
To create a display with a MAX 10 SuperCPLD chip, in this case a MAX1000, there is no memory consumption.
Even more importantly, this exercise only consumes 4% of the space of the 10M08SAU169C8G chip.

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Let's work on the fantastic.
Let's compile for MAX1000.

Let's see what I show for LEDs 0 through 7:
assign LEDS[0]=tested1; //alternate sound every second
assign LEDS[1]=tested2;
assign LEDS[2]=timed; //if a ghost hits, it will time out for one second
assign LEDS[3]=timed; //if a ghost hits, it will time out for one second
assign LEDS[4]=rebote[0]; //bounce on the right and left margins.
assign LEDS[5]=rebote[0]; //bounce on the right and left margins.
assign LEDS[6]=rebote[1];//bounce on the top or bottom margin
assign LEDS[7]=rebote[1];//bounce on the top or bottom margin

In the RTL, we see where the audio data is located.

We proceed to add an HDMI converter to Professor Miguel Angel Rodriguez Jodar's fantastic project at 640x480 and a refresh rate of 60Hz, approximating the pixel clock to 25.2MHz.
https://www.us.es/trabaja-en-la-us/directorio/miguel-angel-rodriguez-jodar

These original sources can be found at:
http://www.forofpga.es/viewtopic.php?f=32&t=40&p=118#p118

Also, when the ghost bounces, it has been removed when it does so with the top and bottom margins and assigns it to a row.
And when it does this with the sides, it assigns it to a column bounce.
By making a logical or between both bounce signals, we have the bounce to calculate with a timer so that the bounce sounds.

I reuse some sounds from other exercises.
These sounds are 8-bit.
The sound lasts 2 seconds since they alternate from the right speaker for 1 second to the left for another second.
If the timing were with the parameter:
parameter CYCLES_2S=14000000;
we move on to:
parameter CYCLES_2S=28000000;

We would see the sound alternating between the left and right speakers when the sound completes after 2 seconds.

I'm uploading this exercise because I'll be using a higher-resolution HDMI file later,
and I have the sound in 8-bit, and I'd like it to be in 16-bit.

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I have trimmed the implementation of Next186 so that it can be a description of 8Kles; it still doesn't boot from SD, but over time it will. I am sharing the sources.

Next186_SoC-max1000.zip

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The well-known game of life in FPGA format has used the available sources from the platform:
https://github.com/marsohod4you/FPGA_game_lifeSince

This could be seen here.

The max1000 only has 8kles, so the size of the board where the game is played, is a quarter of the total, that can be displayed on the screen.

FPGA_game_life-max1000.zip

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This is the correct link of game life:
https://github.com/marsohod4you/FPGA_game_life

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I have trimmed the implementation of Next186 so that it can be a description of 8Kles; it still doesn't boot from SD, but over time it will. I am sharing the sources.

Next186_SoC-max1000.zip

In this video you can see how to port Next186 to HDMI/DVI in MAX1000 8Kles.

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[English]
In this video, a Soviet computer is described, whose schematics were published and assembled from components. It is the Radio-86RK in Russian "Радио-86РК" which initially tried to fit into a MAX FPGA of 4k logic elements, but the description barely exceeds that space of the FPGA, so I choose the 8k logic elements FPGA corresponding to the MAX1000 and assign pins one by one. It shows how easy it is to port descriptions of retro computers when they are described in hardware description languages if an HDMI/DVI output is available. In this description, the pins that take the most time are those associated with the 16-bit SDRAM memory.

[Deustch]
In diesem Video wird ein sowjetischer Computer beschrieben, dessen Schaltpläne veröffentlicht wurden und der aus Komponenten montiert ist. Es handelt sich um den Radio-86RK, auf Russisch "Радио-86РК". Zunächst versuchte ich, ihn in ein FPGA mit maximal 4 KLEs unterzubringen, aber die Beschreibung überschreitet diesen Platzbedarf für das FPGA nur geringfügig. Daher wählte ich das FPGA mit 8 KLEs, das der MAX1000 entspricht, und wies die Pins eins nach dem anderen zu. Es wird gezeigt, wie einfach es ist, Beschreibungen von Retro-Computern zu portieren, da sie in Hardware-Beschreibungssprachen verfasst sind, vorausgesetzt, es steht ein HDMI/DVI-Ausgang zur Verfügung. In dieser Beschreibung sind die Pins, die am meisten Zeit in Anspruch nehmen, die mit dem 16-Bit SDRAM verbunden sind.

[Español]
En este vídeo, se describe un ordenador soviético que se publicaron sus esquemas y se montó por componentes. se trata del Radio-86RK en ruso "Радио-86РК" inicialmente intento que entre en una fga max de 4kles, pero la descripción supera por poco dicho espacio de la FPGA, por lo que escojo la fpga de 8kles que corresponde a la MAX1000, Y asigno pines uno a uno. Mostrando lo fácil que es portar descripciones de ordenadores retro al estar descritos en lenguajes descriptores de hardware si se dispone de una salida HDMI/DVI, en esta descripción los pines que más tiempo llevan son los asociados a la memoria de 16bit sdram.

Radio-86RK-max1000.zip

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original dominic-meads

dvi sinals I - señales dvi I- DVI-Signale I

dvi sinals II - señales dvi II- DVI-Signale II
[Español]
Vamos a adaptar el hdmi de la placa ATLAS o un conector generico hdmi de 8 pines para crear la cara sonriente de "VGA image driver (make a face) on an Intel FPGA"
El código original esta en la siguiente dirección:
https://github.com/dominic-meads/Quartus-Projects/tree/main/VGA_face

Es un ejercicio muy sencillo pero muy util para ver como dibujar en cada cuador de la imagen o "frame" rectángulos.
Para ello se definen coordenadas y desigualdades.

Sólo hay que cambiar la correspondencia de los pines asociados al HDMI y el reloj principal los hacemos paso a paso desde quartus y su pin planner.
El error se ha producido porque primero hay que cambiar de chip al chip usado en la supercpld max1000.

Los pines que hay que cambiar en las restricciones son:

## HDMI Direct ATLAS_V002_MAX1000                                 
set_location_assignment PIN_H5  -to # CLK-               
set_location_assignment PIN_K10 -to # CLK+ # canal del reloj dvi/hdmi
set_location_assignment PIN_H13 -to # 0-  # Negativo difierencial canal azul             
set_location_assignment PIN_J13 -to # 0+  # Positivo canal azul 
set_location_assignment PIN_K11 -to # 1-                 
set_location_assignment PIN_K12 -to # 1+  # canla verde
set_location_assignment PIN_J12 -to # 2-                 
set_location_assignment PIN_L12 -to # 2+  # canal rojo

##clocks ATLAS_V002_MAX1000
set_location_assignment PIN_H6 -to CLK_12MHZ

El envoltorio HDMI es el más simple que he usado y hay que poner a cero las señales negativas.
Es un DVI en realidad y muy sencillo.
Poniendo los pines a 0:
assign TMDS_D0_N=1'b0;
assign TMDS_D1_N=1'b0;
assign TMDS_D2_N=1'b0;
assign TMDS_CLK_N=1'b0;   


Cometimos el error de identificar incorrectamente el chip de la max1000, he puesto la misma familia pero de 2kles, ahora corrigo el error.

La serie max 10 es más moderna que la serie cyclone 10 Lp, sin cambiar las IPS propietarias de intel/altera vamos a ver si sintetiza el diseño para max1000.
Este ejercicio es realmente interesante para saber posicionar elementos en pantalla a través de HDMI/DVI.

[English]
We are going to adapt the HDMI from the ATLAS board or a generic 8-pin HDMI connector to create the smiling face of the "VGA image driver (make a face) on an Intel FPGA." 
The original code is located at the following address: 
https://github.com/dominic-meads/Quartus-Projects/tree/main/VGA_face 

It is a very simple exercise but very useful for seeing how to draw rectangles in each square of the image or "frame." 
Coordinates and inequalities are defined for this purpose. 

You only need to change the mapping of the pins associated with HDMI, and we will set up the main clock step by step from Quartus and its Pin Planner. 
The error occurred because you first need to switch from the chip to the chip used in the SuperCPLD MAX1000. 

The pins that need to be changed in the constraints are:
## HDMI Direct ATLAS_V002_MAX1000                                 
set_location_assignment PIN_H5  -to # CLK-               
set_location_assignment PIN_K10 -to # CLK+ # clock channel
set_location_assignment PIN_H13 -to # 0-                 
set_location_assignment PIN_J13 -to # 0+  # blue channel 
set_location_assignment PIN_K11 -to # 1-                 
set_location_assignment PIN_K12 -to # 1+  # green channel
set_location_assignment PIN_J12 -to # 2-                 
set_location_assignment PIN_L12 -to # 2+  # red channel

##clocks ATLAS_V002_MAX1000set_location_assignment PIN_H6 -to CLK_12MHZ

The HDMI wrapper is the simplest I have used, and the negative signals need to be set to zero.
It is actually a DVI and very simple.Setting the pins to 0:

assign TMDS_D0_N=1'b0;
assign TMDS_D1_N=1'b0;
assign TMDS_D2_N=1'b0;
assign TMDS_CLK_N=1'b0;   

We made the mistake of incorrectly identifying the chip of the max1000; I put the same family but with 2kles, now I am correcting the error.
The max 10 series is more modern than the cyclone 10 LP series. Without changing Intel/Altera's proprietary IPs, let's see if the design synthesizes for max1000.
This exercise is really interesting to know how to position elements on the screen via HDMI/DVI.

[Deutsch]
Wir werden den HDMI-Anschluss der ATLAS-Platine oder einen generischen 8-Pin-HDMI-Stecker anpassen, um das lächelnde Gesicht von ,,VGA-Bildtreiber (ein Gesicht machen) auf einem Intel FPGA" zu erstellen.
Der Originalcode befindet sich unter folgender Adresse:
https://github.com/dominic-meads/Quartus-Projects/tree/main/VGA_face.
Es ist eine sehr einfache, aber sehr nützliche Übung, um zu sehen, wie man Rechtecke in jedem Feld des Bildes oder ,,Frames" zeichnet. Dazu werden Koordinaten und Ungleichungen definiert.
Es müssen nur die Zuordnungen der mit HDMI verbundenen Pins geändert werden, und die Hauptuhr wird Schritt für Schritt über Quartus und seinen Pin Planner eingerichtet.
Der Fehler trat auf, weil man zuerst vom Chip zum verwendeten Chip auf der SuperCPLD MAX1000 wechseln muss. Die Pins, die in den Einschränkungen geändert werden müssen, sind:

## HDMI Direct ATLAS_V002_MAX1000                                 
set_location_assignment PIN_H5  -to # CLK-               
set_location_assignment PIN_K10 -to # CLK+ # positiver Kanal der Taktdifferenz des DVI-Signals
set_location_assignment PIN_H13 -to # 0-                 
set_location_assignment PIN_J13 -to # 0+  # blauer Differenzialkanal 
set_location_assignment PIN_K11 -to # 1-                 
set_location_assignment PIN_K12 -to # 1+  # positiver grün differenzieller Kanal
set_location_assignment PIN_J12 -to # 2-                 
set_location_assignment PIN_L12 -to # 2+  # roter Differenzialkanal 


##clocks ATLAS_V002_MAX1000set_location_assignment PIN_H6 -to CLK_12MHZ

Die HDMI-Hülle ist die einfachste, die ich je benutzt habe, und die negativen Signale müssen auf Null gesetzt werden. Es ist eigentlich ein DVI und sehr einfach. Die Pins auf 0 setzen:

assign TMDS_D0_N=1'b0;
assign TMDS_D1_N=1'b0;
assign TMDS_D2_N=1'b0;
assign TMDS_CLK_N=1'b0;

Wir haben den Fehler gemacht, den Chip des Max1000 falsch zu identifizieren.
Ich habe dieselbe Familie, aber von 2kles, verwendet, jetzt korrigiere ich den Fehler.
Die Max 10-Serie ist moderner als die Cyclone 10 LP-Serie. Ohne die proprietären IPs von Intel/Altera zu ändern, werden wir sehen, ob das Design für Max1000 synthetisiert werden kann.
Diese Übung ist wirklich interessant, um zu lernen, wie man Elemente auf dem Bildschirm über HDMI/DVI positioniert.

CaraSONRIENTE - Limpia - max1000.zip