Playing ZX Spectrum in HDMI in MAX1000 support SDHC 32Gbytes

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Playing great new games:
https://itch.io/s/111036/full-pat-morita-pack

Capture playing Shovel Adventure:
https://youtu.be/uP6nl9aS-cw

New 4Mbytes Sdram to Sram Wrapper:
https://github.com/AtlasFPGA/zx/blob/main/atlas.max/sdram.v

New DVI/HDMI Wrapper in verilog:
https://github.com/AtlasFPGA/zx/blob/main/atlas.max/hdmi.v

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And playing some new demos:
"Elysium State"

"In Color by Darklite and Offence"

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Tutorial, how to port some VHDL opensource cores from reverse U16 - Spanish - you can use translation.

It is a great excersise to knwo how to deal with the VHDL program language and you can see it here.

In next videos I'm going to share how to deal with the serilizer, because MAX10, has a diferent serializer than cyc1000.

In this case i share the ZX48 implementation in VHDL as a .QAR proyect:
https://github.com/AtlasFPGA/U16_ZX_48_Spectrum_Reloj_50MHZ_VHDL

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Using an DVI signal in 24bit color an late runs a ZX Spectrum.

The demo is located here for CYC1000, adapt it to MAX1000, is fairly easy.
https://github.com/AtlasFPGA/Demo_PIOTR.GO_888_DVI

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This is the lines for using the DVI signal, the max 10 with a 55 nanometer achive the frecuencies of a DVI/Digital_video with no problem.

Code Select Expand

set_location_assignment PIN_H6 -to SYS_CLK
set_location_assignment PIN_H5 -to TMDS[0]
set_location_assignment PIN_K10 -to TMDS[1]
set_location_assignment PIN_H13 -to TMDS[2]
set_location_assignment PIN_J13 -to TMDS[3]
set_location_assignment PIN_K11 -to TMDS[4]
set_location_assignment PIN_K12 -to TMDS[5]
set_location_assignment PIN_J12 -to TMDS[6]
set_location_assignment PIN_L12 -to TMDS[7]

You can see the pin planner in the photo added.
It is a nice thing to have a 24 or 30 bit color scheme an consumes a very low count kles.
There is a screenshot also of the compiled piotr-go-vga, but consumes only 8 pins.
In order to reproduce a vga signal with 24bits.
You need:

8 Pins -> Red
8 Pins -> Green
8 Pins -> Blue
1 Pin -> Horizontal Sync
1 Pin -> Vertical Sync

This is the minimal signals you need in vga 8+8+8+1+1=26, but in a digital signal only uses 8 signals, the wrapper used could give 30bits but the implementation only gives 24bits, so 2 signals added for each RGB Color signals.
So for max1000 is more suitable a digital video signal.



You can see the impact in the utilization by entity of using a video signal compatible with DVI.

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With the previous DVI/HDMI pins and the master clock we can create an interesting gradient of color. At a resolution of 1280x1024.

You can translate from this vídeo. I converted the sources from CYC1000 to MAX1000.

The only you need is a HDMI-PMOD, and connect the digital signals with dupont cables.
We need only 8 cables for a DVI/HDMI signal.

I add the sources also for MAX1000.

HDMI-PMOD:


HDMI-SIGNALS:


SCREEN-MAX1000:


SOURCES:
DVI_1280x1024_MAX1000.zip

ORIGINAL SOURCES:
https://github.com/open-design/max10_hdmi/tree/master

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We will rename the signals of the implementation, that uses 24bits of color created by Piotr.go.

Code Select Expand

https://github.com/piotr-go/Lichee-Tang/blob/master/VGA/src/vga.v
To the nomenclature in the previous demo/hdmi demo DVI_1280x1024_max1000.

We visualize the files *.qsf.

VGA.QSF signals:

Code Select Expand

set_location_assignment pin_h6 -to SYS_CLK
set_location_assignment pin_h5 -to TMDS [0]
set_location_assignment pin_k10 -to TMDS [1]
set_location_assignment pin_h13 -to TMDS [2]
set_location_assignment pin_j13 -to TMDS [3]
set_location_assignment pin_k11 -to TMDS [4]
set_location_assignment pin_k12 -to TMDS [5]
set_location_assignment pin_j12 -to TMDS [6]
set_location_assignment pin_l12 -to TMDS [7]

Max10_50.qsf signals:

Code Select Expand

set_location_assignment pin_h6 -to clk12Hz
set_location_assignment pin_h5 -to tmds [0]
set_location_assignment pin_k10 -to tmds [1]
set_location_assignment pin_h13 -to tmds [2]
set_location_assignment pin_j13 -to tmds [3]
set_location_assignment pin_k11 -to tmds [4]
set_location_assignment pin_k12 -to tmds [5]
set_location_assignment pin_j12 -to tmds [6]
set_location_assignment pin_l12 -to tmds [7]

I have made the change of TMDS and SYS_CLK to tmds and CLK12MHz names.

Now change the integrated FPGA.
I proceed to eliminate one by one the assignments of the pins, in pin planner.

I do that because, I want to see the name of the signals.
Let's see if Arrow Blaster is detected.
Appears:

Code Select Expand

USB serial Converter A
USB Serial Converter B

Once the first compilation is finished we enter Pin Planner.
And we see if the name of the signals have been changed.

Next, we will go to all the signs and rename them since we have taken the terminology of the DVI_1280x1024_max1000 screen.
And once the assignments have been changed again, we will proceed to send the flow of data to the Max1000.
And see if the capturer shows the screen_exercise of Piotr.go.

As the signals are seen, they have been renamed, and use the same nomenclature as in the previous screen_exercise.
Once the correspondences of the signals and the pins we rebuilt.

Let's take a walk through the VGA.V file

We will send the data flow to the Max1000.

This exercise is very interesting since it shows how starting from a 640x480 VGA signal with a 60Hz vertical sync.
That makes a 25,175 pixel clock, we visualize the screen at full 24 bits colors, with only 8 HDMI pins.

We will visualize the black box of PPL from intel/altera in the Max 10 family.
We start with a clock from 12MHz.
We approximate by PLL limitations the 25,175MHz Pixel Clock frequency at 25,20000000MHz.
HDMI frequency is 5 times the frequency of pixel clock; that is a 126.00000000MHz Clock.
We visualize that in the Used PLL we could still generate three other frequencies C2, C3. and C4.

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Having already created two different screensaver implementations, we used a VT52 terminal. If you look at the upper left corner, you'll see the seconds. They are slightly faster since, for better visualization in DVI(HDMI, we set a clock of 50.40 MHz, The design uses at first a 50MHz clock as the initial design frequency.

ATLAS Sources:
https://github.com/AtlasFPGA/vt52

Intel/Altera's intellectual properties, such as the phase-locked loop or "PLL," have been approximated to a pixel clock of 25.2 MHz, which gives a resolution of 640x480 with 60Hz vertical synchronization, the exact clock is 25,175Mhz.

You will typically encounter the following errors if you start from a CYCLONE design in families I through IV.
Typically, projects have this configuration:
Single Uncompressed Image (912Kbits UFM)

Let's view the error:
"16031 Current Internal Configuration mode does not support memory initialization or ROM.
Select Internal Configuration mode with ERAM."

This is a memory initialization error.

Now we apply the address and change the parameters.
Assignments - Device - Device and Pin Options - Configuration - Configuration Mode: Single uncompressed image with Memory Initialization
Translate.

The design compilation has been successful.
It is very important that the "IP" intellectual property rights are transferred to the MAX 10 family, given that we have a Max1000 SuperCPLD/FPGA.

Let's begin programming.
And we'll see how the VT52 terminal design shows the seconds of activity in the upper left corner.

I'm slowly translating the comments into other languages.
Greetings.