Pin config for XC6SLX

[vibha_r]

hallo.

I need to configure the b2b pins as RGB888 Hsync and V sync.  for output and 16bit parallel input.
I have to use XC6SLX series. Looking at the user manual. there are pg. 22 . The spcification for the B2B connectors are given i.e J1 and J2. There are lesser SIO pins than DIO pins:

DIO Unrestricted, general-purpose differential user-I/O pin.
SIO Unrestricted, general-purpose user-I/O pin.

How do I use the DIO pins are SIO pins?  I will need a total of
Input : 16 pins for data , 27 pins for adress and 5 control pins.
Output : 8 pins Red ,8 pins Green, 8 pins Blue. 1 Hsync 1 V sync,

Please help. The link for XC6SLX series is
 http://www.trenz-electronic.de/products/fpga-boards/trenz-electronic/gigabee-xc6slx.html

[Oleksandr Kiyenko]

Hello vibha_r
You can use DIO pins as SIO pins.
Only that you need to do is define voltage levels for your input and output signals.
Use IOSTANDARD directive in your UCF file to define single ended signal type.
For example Pin B2B_B2_L57_N is DIO you can use it as SIO adding to UCF file

NET B2B_B2_L57_N  LOC = AB4 | IOSTANDARD = LVCMOS33;

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Regards
Alex

[vibha_r]

thanks Alex. 

One more question :
 I need to define a pin for I/F clock. Which pin should I use : Can I define any DIO or SIo pins as CLk?
Similarly for a CHip select pin also how should I define a pin for CHip Select.

Regards
Vibha

[vibha_r]

One more question :
 I need to define a pin for I/F clock out . Which pin should I use : Can I define any DIO or SIo pins as CLk?
Similarly for a CHip select pin also how should I define a pin for CHip Select.

Regards
Vibha

[Oleksandr Kiyenko]

Hello vibha_r
To better understand, and to create really good project you should read more about FPGA IO resources and clock resources.
For Spartan-6 it will be
Spartan-6 FPGA SelectIO Resources User Guide http://www.xilinx.com/support/documentation/user_guides/ug381.pdf
Spartan-6 FPGA Clocking Resources User Guide http://www.xilinx.com/support/documentation/user_guides/ug382.pdf
If you want short answer:
For clock input you should use GC or CC type FPGA pin (check board schematics to find such pin routed to connector) usually such pins
contain GCLK in name.
As for chip select - usually any pin  can be used for this function, but you should check voltage level. Also if your project is working on
very high frequency it can add some restrictions to select pin for chip select.

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Regards
Alex