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TE0803 PS GTR PLL lock

Started by m1104, September 22, 2023, 02:12:46 PM

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I try to get PS GTR,  PCIe Endpoint working with a FreeRTOS based system. Currently I work in Vitis 2021.2 System Debugger.

I read somewhere that the PS GTR refclk should be stable before POR_B release, so
the idea is to configure the TE0803 Si5338 via I2C in main firmware (not FSBL), then restart the debugging session and hopefully see the GTR PLL lock with a value of 0x10.
But this is not the case. Should that approach be feasible ? At the moment I cannot see the GTR PLL lock. The psu_init.tcl is used as init sequence for the Debug session.

I think the Si5338 should keep the configuration after programming once and no power off, is that correct ?

In Vivado PCIe Ref Clk 2 is selected for the PS GTR, which routes to Si5338 output 3 on TE0803. All outputs currently configured with 100MHz, 1v8, LVDS, SSC., Input IN3/I2C_LSB with 25.0 MHz.

Is there any register to verify the clocking status ?



you can use AMD GTR IBERT to check if GTR looks and you get a stable link:

and yes, as long as you not power of the module SI CLK should be no erased when you has configure it with FSBL