I am working on an SDI passthrough design which requires the utilization of the GT banks for the rx and tx channels and the reference clocks. I found that the pll lock status indicating bit in the cmp_gt_sts[63:0] output signal of the UHDSDI-GT ip indicated a lock failure.
To rule out any error with my SDI design, I generated a much simpler design using clocking wizards (see attached images). The design takes the differential clocks generated by Si5397 on my custom carrier board (later tried with the Si5345 on the SOM as well, same result) and feeds it through the necessary buffers into a clock wizard. I have added counters which are monitored by ILA (these ILAs use a clock generated by the PS). Pin assignments are accurate.
The locked signal of the clock wizard is not asserted and the counters are stuck at zero.
Vitis project has no errors and programs the Si IC without issue. I have verified the clock signals being generated by probing the appropriate capacitors using the oscilloscope.
I tried the same clock wizard design on the ZCU106 board which has the same fpga (xzu7ev). The clock wizard lock signal is asserted and the counters are incremented as expected.
So bottom line, the clock arrives at the fpga without issue but is somehow not detected by the GT banks. I am leaning towards ruling this as an error in the GT banks of the fpga.
Note : The fpga functions perfectly fine for any application that doesnt use GT clocking (UART, Linux build for PS with sample apps, PS ethernet etc.)
Any further tests that I can run to verify whether this is an error in the FPGA? I am looking at purchasing a new SOM if I can verify that is the error. Please let me know if there is anything I may have overlooked.
Am also curious to know whether it is possible for the GT banks to fail (as suspected here) while the fpga functions perfectly fine otherwise. Do share any experience.
