TE0820 eMMC boot Speed

[pema]

Hi there,
I am currently trying to optimize the boot speed from the TE0820. I am booting it from eMMC at 200MHz. Below you find the FSBL debug log.
The FSBL takes 13 secs to load the FIT image( I have everything packed in a .BIN) this is only 41 MB size.

According to xilinx this should take less than 3 secs. Any ideas what it might be wrong ?

Many thanks

Code: [Select]

Xilinx Zynq MP First Stage Boot Loader
Release 2023.1   Aug 14 2023  -  12:29:03
Multiboot FSBL: No
MultiBootOffset: 0x0
Device Name: XCZU3CG
Reset Mode: System Reset
Platform: Silicon (4.0)
--------------   XFsbl_ProcessorInit  -------------- 
Cluster ID 0x80000000
Running on A53-0 (64-bit) Processor, Device Name: XCZU3CG
Proc: A53-0 Freq: 1200000000 Hz Arch: 64
--------------   XFsbl_BoardInit  -------------- 
Processor Initialization Done
--------------   In Stage 2  -------------- 
[INFO] eMMC Boot Mode
SD: rc= 0
File name is BOOT.BIN
[INFO] SD0/eMMC, Freq: 200000000 Hz
[INFO] SD1, Freq: 200000000 Hz
[INFO] Multiboot Reg : 0x0
Image Header Table Offset 0x8C0
*****Image Header Table Details********
Boot Gen Ver: 0x1020000
No of Partitions: 0x6
Partition Header Address: 0x440
Partition Present Device: 0x0
Initialization Success
[INFO] Total Time: 145.390415 ms    : Boot Dev. Init. Time
--------------   In Stage 3, Partition No:1  -------------- 
UnEncrypted data Length: 0x3025
Data word offset: 0x3025
Total Data word length: 0x3025
Destination Load Address: 0xFFFEA000
Execution Address: 0xFFFEA000
Data word offset: 0xF180
Partition Attributes: 0x117
[INFO] Total Time: 16.211010 ms   : P1 Copy time, Size: 49300
Partition 1 Load Success
--------------   In Stage 3, Partition No:2  -------------- 
UnEncrypted data Length: 0x23BD
Data word offset: 0x23BD
Total Data word length: 0x23BD
Destination Load Address: 0x100000
Execution Address: 0x0
Data word offset: 0x121B0
Partition Attributes: 0x116
[INFO] Total Time: 11.063190 ms   : P2 Copy time, Size: 36596
Partition 2 Load Success
--------------   In Stage 3, Partition No:3  -------------- 
UnEncrypted data Length: 0x531C0
Data word offset: 0x531C0
Total Data word length: 0x531C0
Destination Load Address: 0x8000000
Execution Address: 0x8000000
Data word offset: 0x14570
Partition Attributes: 0x114
[INFO] Total Time: 413.541466 ms   : P3 Copy time, Size: 1361664
Partition 3 Load Success
--------------   In Stage 3, Partition No:4  -------------- 
UnEncrypted data Length: 0x9ADBE6
Data word offset: 0x9ADBE6
Total Data word length: 0x9ADBE6
Destination Load Address: 0x10000000
Execution Address: 0x0
Data word offset: 0x67730
Partition Attributes: 0x116
[INFO] Total Time: 12270.523840 ms   : P4 Copy time, Size: 40595352
Partition 4 Load Success
--------------   In Stage 3, Partition No:5  -------------- 
UnEncrypted data Length: 0x300
Data word offset: 0x300
Total Data word length: 0x300
Destination Load Address: 0x20000000
Execution Address: 0x0
Data word offset: 0xA15320
Partition Attributes: 0x116
[INFO] Total Time: 0.978510 ms   : P5 Copy time, Size: 3072
Partition 5 Load Success
All Partitions Loaded
[INFO] Total Time: 13086.604033 ms   (Note: Total execution time includes print times)
--------------   In Stage 4  -------------- 
PM Init Success
Protection configuration applied

from U-Boot show that is not to 8-bit mode but 4-bit.

Code: [Select]

ZynqMP> mmc info
Device: mmc@ff160000
Manufacturer ID: 13
OEM: 4e
Name: Q2J54A
Bus Speed: 199999998
Mode: HS200 (200MHz)
Rd Block Len: 512
MMC version 5.0
High Capacity: Yes
Capacity: 3.6 GiB
Bus Width: 4-bit
Erase Group Size: 512 KiB
HC WP Group Size: 8 MiB
User Capacity: 3.6 GiB WRREL
Boot Capacity: 16 MiB ENH
RPMB Capacity: 512 KiB ENH
Boot area 0 is not write protected
Boot area 1 is not write protected


[M Kirberg]

Hi,

related Xilinx forum posts seem to hint at this is u-boot configuration / devicetree related:

https://support.xilinx.com/s/question/0D52E00006lLwq0SAC/uboot-does-not-switch-emmc-bus-width-to-8bit-mode?language=en_US
https://support.xilinx.com/s/question/0D52E00006hpreDSAQ/emmc-hs200-mode-speed?language=en_US

br

[pema]

Hi  @M Kirberg,
thanks for your prompt reply and support. Yes, I have also already seen those posts. The issue starts in the FSBL and not in the U-Boot.
I have packed currently the BOOT.BIN with: zynqmp_fsbl.elf, pmufw.elf, bl31.elf, system.dtb, u-boot.elf, image.ub, and boot.scr.
As you can see in my previous post the FSBL takes almost 12 sec to load the image.ub ( around 40MB) to SDRAM. This is an eMMC read process. According to Xilinx even in the lowest speed setup should not take more than 2 secs.
https://docs.xilinx.com/r/en-US/ug1085-zynq-ultrascale-trm/Speed-Modes

Mine is taking to load ~39 MB to SDRAM  around 12 secs

Code: [Select]

[INFO] Total Time: 12270.523840 ms   : P4 Copy time, Size: 40595352
That is roughly 3 MB/s . Still far far way from the 25 MB/s(Legacy MMC) or even the 200MB/s(HS200)
 

Code: [Select]

--------------   In Stage 3, Partition No:4  --------------
UnEncrypted data Length: 0x9ADBE6
Data word offset: 0x9ADBE6
Total Data word length: 0x9ADBE6
Destination Load Address: 0x10000000
Execution Address: 0x0
Data word offset: 0x67730
Partition Attributes: 0x116
[INFO] Total Time: 12270.523840 ms   : P4 Copy time, Size: 40595352
Partition 4 Load Success

[M Kirberg]

Hi.

Ok, I did not see you were using the FSBL to load from eMMC.
So you are saying the FSBL eMMC driver is also not fast?

Why do you need to pack image.ub into BOOT.BIN?

Could you also use u-boot itself loading it from eMMC Partition which most likely has much better driver support and might be tunable via devicetree?

[pema]

Yes, you are right the driver support is definitely much better under u-boot.
But I want to use Xilinx Multi-boot and Fallback boot method with single BOOT image.
With this method I can upload several BOOT000x.BIN to the eMMC/SD and the FSBL will manage the multi-boot and fallback. This way I can update the full system (fsbl, pmuf_fw, U-boot, etc etc) with better reliability.

https://docs.xilinx.com/r/en-US/ug1085-zynq-ultrascale-trm/Fallback

[pema]

I just wanted to be sure that under u-boot the speed is better. But not that much better:

Code: [Select]

ZynqMP> mmc info
Device: mmc@ff160000
Manufacturer ID: 13
OEM: 4e
Name: Q2J54A
Bus Speed: 199999998
Mode: HS200 (200MHz)
Rd Block Len: 512
MMC version 5.0
High Capacity: Yes
Capacity: 3.6 GiB
Bus Width: 8-bit
Erase Group Size: 512 KiB
HC WP Group Size: 8 MiB
User Capacity: 3.6 GiB WRREL
Boot Capacity: 16 MiB ENH
RPMB Capacity: 512 KiB ENH
Boot area 0 is not write protected
Boot area 1 is not write protected

ZynqMP> fatload mmc 0:1 0x10000000 BOOT.BIN           
42291136 bytes read in 3057 ms (13.2 MiB/s)
Still not close to 25MB/s

And here from linux

Code: [Select]

# cat /sys/kernel/debug/mmc0/ios
clock: 200000000 Hz
actual clock: 200000000 Hz
vdd: 21 (3.3 ~ 3.4 V)
bus mode: 2 (push-pull)
chip select: 0 (don't care)
power mode: 2 (on)
bus width: 3 (8 bits)
timing spec: 9 (mmc HS200)
signal voltage: 1 (1.80 V)
driver type: 0 (driver type B)

[M Kirberg]

So what is the speed on Linux?

Example (taken from 8-Bit Versal Device)

Code: [Select]

root@petalinux:~# hdparm -tT /dev/mmcblk0

/dev/mmcblk0:
 Timing cached reads:   3188 MB in  2.00 seconds = 1595.96 MB/sec
 Timing buffered disk reads: 278 MB in  3.02 seconds =  91.93 MB/sec
same device performs as 11MB/s in u-boot (4-bit wide)

[pema]

Hi, I get also good speeds there.

Code: [Select]

hdparm -tT /dev/mmcblk0

/dev/mmcblk0:
 Timing cached reads:   1920 MB in  2.00 seconds = 960.58 MB/sec
 Timing buffered disk reads: 268 MB in  3.00 seconds =  89.25 MB/sec
I assume the slow speeds are in FSBL and u-Boot at the moment.

[pema]

Hi
have you ever performed tests at HS200 or HS400 ? If so what modifications are required?
the eMMC and MPSoC supports up to HS200 and HS400 if I am not mistaken
Greetings

[M Kirberg]

Hi,

we have not done this according to my knowledge

According to Zynq Ultrascale+ TRM only HS200 is possible for eMMC:
https://docs.xilinx.com/r/en-US/ug1085-zynq-ultrascale-trm/Speed-Modes?section=XREF_56057_MMC_Different

[pema]

Hi M Kirberg,
thanks for the the feedback. Yes you are right the HS400 is only for the Versal platforms. Still I am not able to run at HS200(8-bits 200MB/s) in the FSBL/U-Boot/Linux.
Ha ve you done any further modifications besides on the  device-tree ? Mine can only run 4-bits

&sdhci0 {
      status = "okay";
      bus-width = <8>;
      clock-frequency = <200000000>;
      max-frequency = <200000000>;
};

[pema]

I have been debugging the FSBL and I get this

Code: [Select]

eg_hostcontrol2: 0xFFC1EFC
HC_Version:2
IsReady:11111111
Card_Version:4
SectorCount:7520256
IsBusy:0
Bus Speed:200000000
CardType:5
Bus Speed Mode: 7
TransferMode: 19
Current BusWidth: 2
Supported BusWidth:4
IsTuningDone: 0
Switch1v8:0
IOU_SLCR MIO_PIN_13:8
IOU_SLCR MIO_PIN_14:8
IOU_SLCR MIO_PIN_15:8
IOU_SLCR MIO_PIN_16:8
IOU_SLCR MIO_PIN_17:8
IOU_SLCR MIO_PIN_18:8
IOU_SLCR MIO_PIN_19:8
IOU_SLCR MIO_PIN_20:8
IOU_SLCR MIO_PIN_21:8
IOU_SLCR MIO_PIN_22:8
IOU_SLCR MIO_PIN_23:8
in the .xsa

Code: [Select]


    /*
    * Register : SD_CONFIG_REG2 @ 0XFF180320

    * Should be set based on the final product usage 00 - Removable SCard Slot
    *  01 - Embedded Slot for One Device 10 - Shared Bus Slot 11 - Reserved
    *  PSU_IOU_SLCR_SD_CONFIG_REG2_SD0_SLOTTYPE                    1

    * 8-bit Support for Embedded Device 1: The Core supports 8-bit Interface 0
    * : Supports only 4-bit SD Interface
    *  PSU_IOU_SLCR_SD_CONFIG_REG2_SD0_8BIT                        1

    * 1.8V Support 1: 1.8V supported 0: 1.8V not supported support
    *  PSU_IOU_SLCR_SD_CONFIG_REG2_SD0_1P8V                        1

    * 3.0V Support 1: 3.0V supported 0: 3.0V not supported support
    *  PSU_IOU_SLCR_SD_CONFIG_REG2_SD0_3P0V                        0

    * 3.3V Support 1: 3.3V supported 0: 3.3V not supported support
    *  PSU_IOU_SLCR_SD_CONFIG_REG2_SD0_3P3V                        1

    * SD Config Register 2
    * (OFFSET, MASK, VALUE)      (0XFF180320, 0x00003384U ,0x00001284U)
    */
PSU_Mask_Write(IOU_SLCR_SD_CONFIG_REG2_OFFSET,
0x00003384U, 0x00001284U);

even though the 8-bit in the .xsa  is set. During the boot this is reset to 0.