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TE0803 GTR Clocking

Started by rkbluecubed, July 25, 2023, 08:09:11 PM

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I would like to connect a Marvell 88E1512 PHY to my Zynq using SGMII via one of the GTR receivers.  This is different from the TEBF0808 reference design which uses RGMII.

The 88E1512 requires a 25 MHz reference clock and internally uses a PLL to generate the necessary 125 MHz. This clock is provided on the CLK125 output pin as LVCMOS (1.8V in my config).  I'd prefer not to have to convert this to differential to feed the B244_CLK0_P/N pins on my TE0803. There are two possible solutions I am considering.

Solution 1: independent clocks

Is is possible to use the TE0803's internal Si5338 clock generator to make a second 125 MHz clock?  Obviously, this wouldn't be phase locked with the 88E1512's clock.  Does SGMII allow for clock frequency mismatch between the two endpoints?

Solution 2: utilize Si5338A built in to the TE0803

An alternate approach that I'm considering is to utilize the CLK0 output on the SI5338A, which is routed to the SoM connector.  The Si5338A could be configured to generate a 25 MHz LVCMOS 1.8V clock that is phase locked to a 125 MHz LVDS clock.  An example Si5338A config is attached.

Any advice would be appreciated.  I'm currently leaning towards Solution 2 because of the lower BOM cost.


sorry for late reply.
both solutions are possible. But solution 1 should be enough.

  • separate oscilator for 25MHz CLK of the ETH PHY
  • 125MHz CLK from SI5338 for GTR

SI5338 can be reprogrammed on runtime. We do this via FSBL on our starterkit reference designs. You can reuse the code and exchange the SI configuration header with your configuration.