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DDR3 SDRAM of XC6SLX series

Started by vibha_r, January 11, 2012, 10:56:36 AM

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vibha_r

hallo ,

want to know how to program the DDR3 SDRAM of XC6SLX series. There is no documentation regarding the address space occupied by the DDR3 SDRAM. How is the programming of this generally done?

http://www.trenz-electronic.de/products/fpga-boards/trenz-electronic/gigabee-xc6slx.html


Regards.

Ales Gorkic

#1
Dear Vibha,

We provide AXI reference design for the module where you can access the memory with Microblaze and DMAs:
https://github.com/Trenz-Electronic/TE060X-GigaBee-Reference-Designs/

There is also low level MIG design, where you can access memory via HDL.

Best regards,

Ales


vibha_r

thanks .

I have another question . Not regarding the DDR SDRAM. It is related to block RAM. How do I store data and read back data from Block Ram. Should not there be aaddress space and also the I/O pins specified for block RAM . I am unable to find that.

Regards

Vibha Rao.

Ales Gorkic

Hi Vibha,

The BRAM for processor always starts at adress 0x00000000. The high adress of this space defines how much BRAM is used for processor.

Best regards,

Ales