Trenz Electronic Products > Trenz Electronic FPGA Modules
TE0790 under virtual box Ubuntu Guest
(1/1)
pema:
Hi there,
this is most likely a issue caused by VirtualBox rather than the TE0790. But perhaps someone is experiencing the same issue and knows a work around.
Since I perform most of the development under a virtual machine, I would also like to have access to the JTAG probe under Linux virtual machine.
The problem:
When I connect the TE0790 to the VM I am able to connect through the xsdb or xsct but not able to list the targets( bellow you find the output).
--- Code: ---ubuntu@ubuntu-VirtualBox:~$ lsusb
Bus 001 Device 003: ID 0403:6010 Future Technology Devices International, Ltd FT2232C/D/H Dual UART/FIFO IC
Bus 001 Device 001: ID 1d6b:0001 Linux Foundation 1.1 root hub
ubuntu@ubuntu-VirtualBox:~$ xsdb
rlwrap: warning: your $TERM is 'xterm-256color' but rlwrap couldn't find it in the terminfo database. Expect some problems.
****** System Debugger (XSDB) v2023.1
**** Build date : May 7 2023-15:13:35
** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
** Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
xsdb% connect
attempting to launch hw_server
****** Xilinx hw_server v2023.1
**** Build date : May 7 2023 at 15:13:34
** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
** Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
INFO: hw_server application started
INFO: Use Ctrl-C to exit hw_server application
INFO: To connect to this hw_server instance use url: TCP:127.0.0.1:3121
tcfchan#0
xsdb% targets
xsdb%
--- End code ---
Under Windows Host this does not happens:
--- Code: ---C:\Xilinx\Vitis\2022.2\bin
λ .\xsct
****** Xilinx Software Commandline Tool (XSCT) v2022.2.0
**** SW Build 0 on 2022-10-13-12:09:39
** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
xsct% connect
tcfchan#0
xsct% targets
1 PS TAP
2 PMU
3 PL
4 PSU
5 RPU (Reset)
6 Cortex-R5 #0 (RPU Reset)
7 Cortex-R5 #1 (RPU Reset)
8 APU (L2 Cache Reset)
9 Cortex-A53 #0 (APU Reset)
10 Cortex-A53 #1 (APU Reset)
xsct%
--- End code ---
Anyone having the same issue? I can of course be always switching between VM and Host to developt and flash or debug. But like I said is quite tedius to switch between both.
Greetings
JH:
Hi,
as I know this can happens and I didn't have a solution.
Here they recommend to install cable drivers again:
https://support.xilinx.com/s/question/0D52E00006hphZuSAI/jtag-not-working-on-virtual-box-ubuntu-1604?language=en_US
I use AMD(Xilinx) tools with WSL:
https://wiki.trenz-electronic.de/display/PD/AMD+Tools+and+Win10+WSL
In this case there is there is a trick, which maybe also works on virtual box(but I didn't expect it).
Start HW_Manager.exe on WinOS (C:\Xilinx\Vivado\<vivado version>\bin\unwrapped\win64.o\hw_server.exe). In case the server is running, Vivado from WSL automatically connect to the HW server and JTAG is availabe.
br
John
pema:
Hi John,
many thanks for your reply .
I am posting here a solution that worked for me... for posterity :-)
All you need is either Xilinx Vivado/Vitis or petalinux in my case.
--- Code: ---$ cd ~/petalinux/2022.2/tools/xsct/data/xicom/cable_drivers/lin64/install_script/
$ sudo ./install_drivers
$ sudo ./setup_pcusb
$ sudo su -
$ cd /etc/udev/rules.d
$ sed -i -e 's/MODE=/MODE:=/g' 52-xilinx*.rules
$ exit
$ sudo udevadm control --reload
#optional
$ echo "alias xsct="$HOME"/./petalinux/2022.2/tools/xsct/bin/xsct" >> ~/.bashrc
$ echo "alias xsct="$HOME"/./petalinux/2022.2/tools/xsct/bin/xsdb" >> ~/.bashrc
--- End code ---
Test it.
--- Code: ---$ xsct
rlwrap: warning: your $TERM is 'xterm-256color' but rlwrap couldn't find it in the terminfo database. Expect some problems.
****** Xilinx Software Commandline Tool (XSCT) v2022.2.0
**** SW Build 0 on 2022-10-05-18:51:07
** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
WARNING: sdtgen package cannot be loaded. System Device tree commands will not
be available
xsct% connect
tcfchan#0
xsct% targets
1 PS TAP
2 PMU
3 PL
4 PSU
5 RPU (Reset)
6 Cortex-R5 #0 (RPU Reset)
7 Cortex-R5 #1 (RPU Reset)
8 APU (L2 Cache Reset)
9 Cortex-A53 #0 (APU Reset)
10 Cortex-A53 #1 (APU Reset)
--- End code ---
Navigation
[0] Message Index
Go to full version