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GbE PHY on TE0706

Started by GuinnessTrinker, April 14, 2023, 09:45:41 AM

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I am trying to build a MicroBlaze-Design using the PHY 88E1512 on Baseboard and AXI_Ethernet with DMA on Module.
Receiving datas from external PC is working fine, but the PC does not detect any incoming datas (zero bytes) (Status network-adapter in Windows systemconfiguration).
Comunnication with the PHY over MDIO is working fine.

I do not use Linux, but StandAlone/Baremetall-SW.

Are there any settings on the baseboard I need?
What could I do to get it work?


I also tried all possible combinations of enable/disable RGMII Delay Timing of TX_CLK Delay and RX_CLK Delay in PHY-Register 21 in page 2


All rgmii_0_* ports are configured to IOSTANDARD LVCMOS18.
VCCIO13 is connected to JM2.1 and .3 == JB2.2 and .4 on TE0706 == 1.8V according to schematics

phy_config is connected to xlconstant (value= 1) => VDDO =>  PHYAD[0] = 1, VDDO_LEVEL = 3.3V/1.8V


we have only an example with TE0720, maybe this helps a little bit(check constrains):

AXI_Ethernet with DMA is not free available and we didn't test this IP on this combination.

There is also one 0Ohm resitor which should be removed(depends on the IP which us used):


Hi JH,
thanks for your help.
After some time of google-searching I found the solution.

Constraints were my first thought too, but all needed rules are already declared inside TEMAC Ip-core.
Trenz layouts (both TE0706 and TE0712) are fine. No need for further attention.

The "only" thing to do is to patch lwip inside Vitis.

This link is public. So I think it is allowed to post:

LWIP needs patches for
- detecting RGMII-PHY Marvel 88E151x.
- configure delays on RGMII-bus
- auto-negotiation

We want to replace Trenz-Modul Spartan-6 "TE0600".
TE0712 is a good option to do so.

Yes, you need a license for TEMAC / Axi_Ethernet IP-Core.
(as on Spartan too)


I am glad to hear that it now works for you, and thank you for sharing your solution here.