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TE0720 Ethernet to PL - IO placement error

Started by ol_egg, March 13, 2023, 11:17:58 AM

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I'am using a TE0720 and want to get the raw ethernet data via ETH0 into the PL. The custom carrier board has the RJ45 jack connected to ETH0.
The ETH0 is configured to use EMIOs.
In the block design there is a gmii_to_rgmii block whose pins are made external for the connection with the PHY.

The XDC-files are based on the "test_board" reference design with additional constraints added for ethernet and other stuff.

The point I'm stuck on is here:

[Place 30-58] IO placement is infeasible. Number of unplaced IO Ports (6) is greater than number of available sites (0).
The following are banks with available pins:
IO Group: 0 with : SioStd: LVCMOS18   VCCO = 1.8 Termination: 0  TermDir:  In   RangeId: 1 IdelayId: 1 BufioId: 1  has only 0 sites available on device, but needs 5 sites.
Term: rgmii_rxd_0[0]
Term:  rgmii_rxd_0[1]
Term:  rgmii_rxd_0[2]
Term:  rgmii_rxd_0[3]
Term:  rgmii_rx_ctl_0

IO Group: 2 with : SioStd: LVCMOS18   VCCO = 1.8 Termination: 0  TermDir:  Out  RangeId: 1 Drv: 12  has only 0 sites available on device, but needs 6 sites.
Term:  rgmii_txd_0[0]
Term:  rgmii_txd_0[1]
Term:  rgmii_txd_0[2]
Term:  rgmii_txd_0[3]
Term:  rgmii_tx_ctl_0
Term:  and rgmii_txc_0

My questions are:

1) Is it basically possible to get the ethernet data via EMIO from PHY to PL instead of using the MIO + software way?

2) Can I workaround the IO placement error or are the banks simply too occupied?

I'm new to the "Zynq-world", so please be patient with me ;)

Best regards


onboard eth phy is connected to MIO.  You can change controller to PL but not pcb connection.....PS configuration depends on HW configuration on the PCB!
You can use TE0720 together with TE0706 carrier. TE0706 has separte Gbit ETH PHY which is accessible via PL...I think, that's what you need.
We have also an older demo design for this combination: